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參數(shù)資料
型號(hào)： AD7714ARS-5
廠商： ANALOG DEVICES INC
元件分類： ADC
英文描述： 3 V/5 V, CMOS, 500 uA Signal Conditioning ADC
中文描述： 5-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO28
封裝： SSOP-28
文件頁數(shù)： 4/40頁
文件大小： 306K
代理商： AD7714ARS-5
AD7714–SPECIFICATIONS
(AD7714-5); REFIN(–) = AGND; MCLKIN = 1MHz to 2.4576MHz unless otherwise noted. All specifications T
MIN
to T
MAX
unless otherwise noted.)
Parameter
A Versions
Units
Conditions/Comments
TRANSDUCER BURNOUT
14
Current
Initial Tolerance
Drift
1
±
10
0.1
μ
A nom
% typ
%/
°
C typ
SYSTEM CALIBRATION
Positive Full-Scale Calibration Limit
15
Negative Full-Scale Calibration Limit
15
Offset Calibration Limit
16
Input Span
16
(1.05
×
V
REF
)/GAIN
–(1.05
×
V
REF
)/GAIN
–(1.05
×
V
REF
)/GAIN
0.8
×
V
REF
/GAIN
(2.1
×
V
REF
)/GAIN
V max
V max
V max
V min
V max
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
POWER REQUIREMENTS
Power Supply Voltages
AV
DD
Voltage (AD7714-3)
AV
DD
Voltage (AD7714-5)
DV
DD
Voltage
Power Supply Currents
AV
DD
Current
+3 to +3.6
+4.75 to +5.25
+3 to +5.25
V
V
V
For Specified Performance
For Specified Performance
For Specified Performance
AV
DD
= 3.3V or 5V. BST Bit of Filter High Register = 0
17
Typically 0.2 mA. BUFFER = 0 V. f
CLK IN
= 1MHz or 2.4576MHz
Typically 0.4 mA. BUFFER = DV
DD
. f
CLK IN
= 1MHz or 2.4576MHz
AV
DD
= 3.3V or 5V. BST Bit of Filter High Register = 1
17
Typically 0.3mA. BUFFER = 0V. f
CLK IN
= 2.4576MHz
Typically 0.8mA. BUFFER = DV
DD
. f
CLK IN
= 2.4576MHz
Digital I/Ps = 0V or DV
DD.
External MCLK IN
Typically 0.15mA. DV
DD
= 3.3V. f
CLK IN
= 1MHz
Typically 0.3mA. DV
DD
= 5V. f
CLK IN
= 1MHz
Typically 0.4mA. DV
DD
= 3.3V. f
CLK IN
= 2.4576MHz
Typically 0.6mA. DV
DD
= 5V. f
CLK IN
= 2.4576MHz
0.27
0.6
mA max
mA max
0.5
1.1
mA max
mA max
DV
DD
Current
18
0.23
0.4
0.5
0.8
See Note 20
mA max
mA max
mA max
mA max
dB typ
Power Supply Rejection
19
Normal-Mode Power Dissipation
18
AV
DD
= DV
DD
= +3.3V. Digital I/Ps = 0V or DV
DD
. External MCLK IN
Typically 1.25mW. BUFFER = 0V. f
CLK IN
= 1MHz. BST Bit = 0
Typically 1.8mW. BUFFER = +3.3V. f
CLK IN
= 1MHz. BST Bit = 0
Typically 2mW. BUFFER = 0V. f
CLK IN
= 2.4576MHz. BST Bit = 0
Typically 2.6mW. BUFFER = +3.3V. f
CLK IN
= 2.4576MHz. BST Bit = 0
AV
DD
= DV
DD
= +5V. Digital I/Ps = 0V or DV
DD
. External MCLK IN
Typically 2.5mW. BUFFER = 0V. f
CLK IN
= 1MHz. BST Bit = 0
Typically 3.5mW. BUFFER = +5V. f
CLK IN
= 1MHz. BST Bit = 0
Typically 4mW. BUFFER = 0V. f
CLK IN
= 2.4576MHz. BST Bit = 0
Typically 5mW. BUFFER = +5V. f
CLK IN
= 2.4576MHz. BST Bit = 0
External MCLK IN = 0 V or DV
DD
. Typically 20
μ
A. V
DD
= +5 V
External MCLK IN = 0 V or DV
DD
. Typically 5
μ
A. V
DD
= +3.3 V
1.65
2.75
2.55
3.65
mW max
mW max
mW max
mW max
Normal-Mode Power Dissipation
3.35
5
5.35
7
40
10
mW max
mW max
mW max
mW max
μ
A max
μ
A max
Standby (Power-Down) Current
21
Standby (Power-Down) Current
21
NOTES
15
After calibration, if the input voltage exceeds positive full scale, the converter will output all 1s. If the input is less than negative full scale, then the device outputs all 0s.
16
These calibration and span limits apply provided the absolute voltage on the analog inputs does not exceed AV
DD
+ 30mV or go more negative than AGND–30mV. The
offset calibration limit applies to both the unipolar zero point and the bipolar zero point.
17
For higher gains (
≥
8) at f
CLKIN
= 2.4576MHz, the BST bit of the Filter High Register must be set to 1. For other conditions, it can be set to 0.
18
When using a crystal or ceramic resonator across the MCLK pins as the clock source for the device, the DV
DD
current and power dissipation will vary depending on the crystal
or resonator type (see Clocking and Oscillator Circuit section).
19
Measured at dc and applies in the selected passband. PSRR at 50 Hz will exceed 120 dB with filter notches of 5 Hz, 10 Hz, 25 Hz or 50 Hz. PSRR at 60 Hz will exceed 120 dB
with filter notches of 6 Hz, 10 Hz, 30 Hz or 60 Hz.
20
PSRR depends on gain. For Gain of 1 : 70 dB typ: For Gain of 2 : 75 dB typ; For Gain of 4 : 80 dB typ; For Gains of 8 to 128 : 85 dB typ.
21
If the external master clock continues to run in standby mode, the standby current increases to 150
μ
A typical with 5 V supplies and 75
μ
A typical with 3.3 V supplies. When
using a crystal or ceramic resonator across the MCLK pins as the clock source for the device, the internal oscillator continues to run in standby mode and the power dissipation
depends on the crystal or resonator type (see Standby Mode section).
Specifications subject to change without notice.
(AV
DD
= + 3.3V to +5V, DV
DD
= +3.3V to +5V, REF IN(+) = +1.25V (AD7714-3) or +2.5V
REV. C
–4–
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