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| 型號： | AD7714YR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 3 V/5 V, CMOS, 500 uA Signal Conditioning ADC |
| 中文描述： | 5-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO24 |
| 封裝： | WSOIC-24 |
| 文件頁數(shù)： | 18/40頁 |
| 文件大小： | 306K |
| 代理商： | AD7714YR |
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AD7714
REV. C
–18–
Test Register (RS2–RS0 = 1, 0, 0)
The part contains a Test Register which is used in testing the device. The user is advised not to change the status of any of the bits in this
register from the default (Power-On or RESET) status of all 0s as the part will be placed in one of its test modes and will not operate cor-
rectly. If the part enters one of its test modes, exercising
RESET
will exit the part from the mode. An alternative scheme for getting the
part out of one of its test modes, is to reset the interface by writing 32 successive 1s to the part and then write all 0s to the Test Register.
Data Register (RS2–RS0 = 1, 0, 1)
The Data Register on the part is a read-only register which contains the most up-to-date conversion result from the AD7714. The
register can be programmed to be either 16-bits or 24-bits wide, determined by the status of the WL bit of the Mode Register. If the
Communications Register data sets up the part for a write operation to this register, a write operation must actually take place in
order to return the part to where it is expecting a write operation to the Communications Register (the default state of the interface).
However, the 16 or 24 bits of data written to the part will be ignored by the AD7714.
Zero-Scale Calibration Register (RS2–RS0 = 1, 1, 0); Power On/Reset Status: 1F4000Hex
The AD7714 contains three zero-scale calibration registers, labelled Zero-Scale Calibration Register 0 to Zero Scale Calibration
Register2. The three registers are totally independent of each other such that in fully differential mode there is a zero-scale register
for each of the input channels. Each of these registers is a 24-bit read/write register and, when writing to the registers, 24 bits must be
written; otherwise no data will be transferred to the register. The register is used in conjunction with the associated full-scale calibra-
tion register to form a register pair. These register pairs are associated with input channel pairs as outlined in Table VII.
While the part is set up to allow access to these registers over the digital interface, the part itself no longer has access to the register
coefficients to correctly scale the output data. As a result, there is a possibility that after accessing the calibration registers (either read
or write operation) the first output data read from the part may contain incorrect data. In addition, a read or write operation to the
calibration register should not be attempted while a calibration is in progress. These eventualities can be avoided by taking either the
SYNC
input low or the FSYNC bit of the Mode Register high before the calibration register operation and taking them either high or
low respectively after the operation is complete.
Full-Scale Calibration Register (RS2–RS0 = 1, 1, 1); Power On/Reset Status: 5761ABHex
The AD7714 contains three full-scale calibration registers, labelled Full-Scale Calibration Register 0 to Full-Scale Calibration Regis-
ter 2. The three registers are totally independent of each other such that in fully differential mode there is a full-scale register for each
of the input channels. Each of these registers is a 24-bit read/write register and, when writing to the registers, 24 bits must be written,
otherwise no data will be transferred to the register. The register is used in conjunction with the associated zero-scale calibration
register to form a register pair. These register pairs are associated with input channel pairs as outlined in TableVII.
While the part is set up to allow access to these registers over the digital interface, the part itself no longer has access to the coeffi-
cients to correctly scale the output data. As a result, there is a possibility that after accessing the calibration registers (either read or
write operation) the first output data read from the part may contain incorrect data. In addition, a read or write operation to the
calibration register should not be attempted while a calibration is in progress. These eventualities can be avoided by taking either the
SYNC
input low or the FSYNC bit of the Mode Register high before the calibration register operation and taking them either high or
low respectively after the operation is complete.
CALIBRATION OPERATIONS
The AD7714 contains a number of calibration options as outlined previously. Table XI summarizes the calibration types, the opera-
tions involved and the duration of the operations. There are two methods of determining the end of calibration. The first is to moni-
tor when
DRDY
returns low at the end of the sequence.
DRDY
not only indicates when the sequence is complete but also that the
part has a valid new sample in its data register. This valid new sample is the result of a normal conversion which follows the calibra-
tion sequence. The second method of determining when calibration is complete is to monitor the MD2, MD1 and MD0 bits of the
Mode Register. When these bits return to 0, 0, 0 following a calibration command, it indicates that the calibration sequence is com-
plete. This method does not give any indication of there being a valid new result in the data register. However, it gives an earlier
indication that calibration is complete than
DRDY
. The time to when the Mode Bits (MD2, MD1 and MD0) return to 0, 0, 0
represents the duration of the calibration. The sequence to when
DRDY
goes low also includes a normal conversion and a pipeline
delay, t
P
(2000
×
t
CLK IN
), to correctly scale the results of this first conversion. The time for both methods is given in the table.
Table XI. Calibration Operations
Calibration Type
Self Calibration
MD2, MD1, MD0
0, 0, 1
Calibration Sequence
Internal ZS Cal @ Selected Gain +
Internal FS Cal @ Selected Gain
ZS Cal on AIN @ Selected Gain
FS Cal on AIN @ Selected Gain
ZS Cal on AIN @ Selected Gain +
Internal FS Cal @ Selected Gain
Internal ZS Cal @ Selected Gain +
Normal Conversion
Internal ZS Cal @ Selected Gain
Internal FS Cal @ Selected Gain
Duration to Mode Bits
6
×
1/Output Rate
Duration to
DRDY
9
×
1/Output Rate + t
p
ZS System Calibration
FS System Calibration
System-Offset Calibration
0, 1, 0
0, 1, 1
1, 0, 0
3
×
1/Output Rate
3
×
1/Output Rate
6
×
1/Output Rate
4
×
1/Output Rate + t
P
4
×
1/Output Rate + t
P
9
×
1/Output Rate + t
P
Background Calibration
1, 0, 1
Bits Not Reset
6
×
1/Output Rate
ZS Self Calibration
FS Self Calibration
1, 1, 0
1, 1, 1
3
×
1/Output Rate
3
×
1/Output Rate
6
×
1/Output Rate + t
P
6
×
1/Output Rate + t
P
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