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參數資料
| 型號： | AD7715ARU-5 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | AB 4C 4#12 PIN RECP |
| 中文描述： | 1-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO16 |
| 封裝： | MO-153AB, TSSOP-16 |
| 文件頁數： | 19/31頁 |
| 文件大小： | 474K |
| 代理商： | AD7715ARU-5 |
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AD7715
–19–
REV. C
and gain that can be accommodated by the part is the require-
ment that the positive full-scale calibration limit is
≤
1.05
×
V
REF
/GAIN. This allows the input range to go 5% above the
nominal range. The in-built headroom in the AD7715’s analog
modulator ensures that the part will still operate correctly with a
positive full-scale voltage which is 5% beyond the nominal.
The range of input span in both the unipolar and bipolar modes
has a minimum value of 0.8
×
V
REF
/GAIN and a maximum
value of 2.1
×
V
REF
/GAIN. However, the span (which is the
difference between the bottom of the AD7715’s input range and
the top of its input range) must take into account the limitation
on the positive full-scale voltage. The amount of offset that can
be accommodated depends on whether the unipolar or bipolar
mode is being used. Once again, the offset must take into ac-
count the limitation on the positive full-scale voltage. In unipo-
lar mode, there is considerable flexibility in handling negative
(with respect to AIN(–)) offsets. In both unipolar and bipolar
modes, the range of positive offsets which can be handled by the
part depends on the selected span. Therefore, in determining
the limits for system zero-scale and full-scale calibrations, the
user has to ensure that the offset range plus the span range does
exceed 1.05
×
V
REF
/GAIN. This is best illustrated by looking at
a few examples.
If the part is used in unipolar mode with a required span of
0.8
×
V
REF
/GAIN, then the offset range which the system cali-
bration can handle is from –1.05
×
V
REF
/GAIN to +0.25
×
V
REF
/
GAIN. If the part is used in unipolar mode with a required span of
V
REF
/GAIN, then the offset range which the system calibration can
handle is from –1.05
×
V
REF
/GAIN to +0.05
×
V
REF
/GAIN. Simi-
larly, if the part is used in unipolar mode and required to re-
move an offset of 0.2
×
V
REF
/GAIN, then the span range which
the system calibration can handle is 0.85
×
V
REF
/GAIN.
If the part is used in bipolar mode with a required span of
±
0.4
×
V
REF
/GAIN, then the offset range which the system cali-
bration can handle is from –0.65
×
V
REF
/GAIN to +0.65
×
V
REF
/
GAIN. If the part is used in bipolar mode with a required span
of
±
V
REF
/GAIN, then the offset range which the system calibra-
tion can handle is from –0.05
×
V
REF
/GAIN to +0.05
×
V
REF
/
GAIN. Similarly, if the part is used in bipolar mode and required
to remove an offset of
±
0.2
×
V
REF
/GAIN, then the span range
which the system calibration can handle is
±
0.85
×
V
REF
/GAIN.
Power-Up and Calibration
On power-up, the AD7715 performs an internal reset that sets
the contents of the internal registers to a known state. There
are default values loaded to all registers after a power-on or
reset. The default values contain nominal calibration coefficients
for the calibration registers. However, to ensure correct calibra-
tion for the device a calibration routine should be performed
after power-up.
The power dissipation and temperature drift of the AD7715 are
low, and no warm-up time is required before the initial calibra-
tion is performed. However, if an external reference is being
used, this reference must have stabilized before calibration is
initiated. Similarly, if the clock source for the part is generated
from a crystal or resonator across the MCLK pins, the start-up
time for the oscillator circuit should elapse before a calibration
is initiated on the part (see below).
USING THE AD7715
Clocking and Oscillator Circuit
The AD7715 requires a master clock input, which may be an
external CMOS compatible clock signal applied to the MCLKIN
pin with the MCLKOUT pin left unconnected. Alternatively, a
crystal or ceramic resonator of the correct frequency can be
connected between MCLKIN and MCLKOUT in which case
the clock circuit will function as an oscillator, providing the
clock source for the part. The input sampling frequency, the
modulator sampling frequency, the –3dB frequency, output
update rate and calibration time are all directly related to the
master clock frequency, f
CLKIN
. Reducing the master clock
frequency by a factor of 2 will halve the above frequencies and
update rate and double the calibration time. The current drawn
from the DV
DD
power supply is also directly related to f
CLKIN
.
Reducing f
CLKIN
by a factor of 2 will halve the DV
DD
current
but will not affect the current drawn from the AV
DD
power
supply.
Using the part with a crystal or ceramic resonator between the
MCLK IN and MCLK OUT pins generally causes more cur-
rent to be drawn from DV
DD
than when the part is clocked from
a driven clock signal at the MCLK IN pin. This is because the
on-chip oscillator circuit is active in the case of the crystal or
ceramic resonator. Therefore, the lowest possible current on
the AD7715 is achieved with an externally applied clock at the
MCLK IN pin with MCLK OUT unconnected and unloaded.
The amount of additional current taken by the oscillator de-
pends on a number of factors—first, the larger the value of
capacitor placed on the MCLKIN and MCLKOUT pins, then
the larger the DV
DD
current consumption on the AD7715. Care
should be taken not to exceed the capacitor values recommended
by the crystal and ceramic resonator manufacturers to avoid
consuming unnecessary DV
DD
current. Typical values recom-
mended by crystal or ceramic resonator manufacturers are in the
range of 30pF to 50pF, and if the capacitor values on MCLK
IN and MCLK OUT are kept in this range, they will not result
in any excessive DV
DD
current. Another factor that influences
the DV
DD
current is the effective series resistance (ESR) of the
crystal which appears between the MCLK IN and MCLK OUT
pins of the AD7715. As a general rule, the lower the ESR value
then the lower the current taken by the oscillator circuit.
When operating with a clock frequency of 2.4576MHz, there is
50
μ
A difference in the DV
DD
current between an externally
applied clock and a crystal resonator when operating with a
DV
DD
of +3V. With DV
DD
= +5V and f
CLK IN
= 2.4576MHz,
the typical DV
DD
current increases by 200
μ
A for a crystal/
resonator supplied clock versus an externally applied clock. The
ESR values for crystals and resonators at this frequency tend to
be low and as a result there tends to be little difference between
different crystal and resonator types.
When operating with a clock frequency of 1MHz, the ESR value
for different crystal types varies significantly. As a result, the DV
DD
current drain varies across crystal types. When using a crystal
with an ESR of 700
or when using a ceramic resonator, the
increase in the typical DV
DD
current over an externally-applied
clock is 50
μ
A with DV
DD
= +3V and 175
μ
A with DV
DD
=
+5V. When using a crystal with an ESR of 3k
, the increase in
the typical DV
DD
current over an externally applied clock is
100
μ
A with DV
DD
= +3V and 400
μ
A with DV
DD
= +5V.
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