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參數資料
| 型號： | AD7718BR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 8-/10-Channel, Low Voltage, Low Power, ADCs |
| 中文描述： | 10-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO28 |
| 封裝： | PLASTIC, SOIC-28 |
| 文件頁數： | 37/44頁 |
| 文件大小： | 339K |
| 代理商： | AD7718BR |
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REV. 0
AD7708/AD7718
–37–
Analog Input Channels
The input multiplexer on AD7708/AD7718 can be configured
as either an 8- or 10-input channel device. This configuration is
selected using the CHCON bit in the MODE register. With
CHCON = 0 (Figure 23), the user has eight input channels; these
can be configured as eight pseudo-differential input channels with
respect to AINCOM or four fully-differential input channels.
In this configuration the user can select REFIN1 or REFIN 2 as
the reference for the selected channel using the REFSEL bit in
the mode register.
AIN6
AIN5
AIN4
AIN3
AIN2
AIN1
AD7708/
AD7718
AIN8
AIN7
REFIN1(+)
AINCOM
REFIN1(
–
)
REFIN2(+)
REFIN2(
–
)
AIN6
AIN5
AIN4
AIN3
AIN2
AIN1
AIN8
AIN7
REFIN1(+)
AINCOM
REFIN1(
–
)
REFIN2(+)
REFIN2(
–
)
Figure 23. Analog Input and Reference Options with
CHCON = 0
With CHCON = 1 (Figure 24), the user has 10 input channels
that can be configured as 10 pseudo-differential input channels
with respect to AINCOM or as five fully-differential input chan-
nels. The contents of the CHCON bit overrides the REFSEL
bit. If the ADC is configured in five fully-differential or 10 pseudo-
differential input channel mode, the REFSEL bit setting is
irrelevant as only REFIN1 is available. Channel selection Bits
CH3, CH2, CHI, and CH0 in the ADCCON register select the
input channel.
The input multiplexer switches the selected input channel to the
on-chip buffer amplifier and sigma-delta converter. When the
analog input channel is switched, the settling time of the part
must elapse before a new valid word is available from the ADC.
If any two inputs are configured as a differential input pair, this
input is buffered and the common-mode and absolute input volt-
age is restricted to a range between AGND + 100 mV and AV
DD
– 100 mV. Care must be taken in setting up the common-mode
voltage and input voltage range to ensure that these limits are
not exceeded, otherwise there will be a degradation in linearity
and noise performance.
AIN6
AIN5
AIN4
AIN3
AIN2
AIN1
AD7708/
AD7718
AIN8
AIN7
REFIN1(+)
AINCOM
REFIN1(
–
)
AIN9
AIN10
AIN6
AIN5
AIN4
AIN3
AIN2
AIN1
AIN8
AIN7
REFIN1(+)
AINCOM
REFIN1(
–
)
AIN9
AIN10
Figure 24. Analog Input and Reference Options with
CHCON = 1
Single-Ended Operation
The NEGBUF bit in the mode register is used to control the
operation of the input buffer on the AINCOM pin when config-
ured for pseudo-differential mode of operation. If cleared, the
analog negative input (AINCOM) is unbuffered. It should be
noted that the unbuffered input path on the AINCOM provides
a dynamic load to the driving source. Therefore, resistor/capacitor
combinations on this input pin can cause dc gain errors depend-
ing on the output impedance of the source that is driving the
AINCOM input. AINCOM is tied to AGND for single-ended
operation. This enables all pseudo-differential inputs to act as
single-ended analog inputs. All analog inputs still operate in
buffered mode and their common-mode and absolute input
voltage is restricted to a range between AGND + 100 mV and
AV
DD
– 100 mV.
Chop Mode of Operation (
CHOP
= 0)
The signal chain on the AD7708/AD7718 can be operated with
chopping enabled or disabled. Chopping is enabled or disabled
using the
CHOP
bit in the mode register. The default mode of
operation is for chop enabled (
CHOP
= 0). Optimum perfor-
mance in terms of minimizing offset error and offset and gain
drift performance is achieved when chopping is enabled. The
digital filter decimation rate, and consequently the output data
rate, is programmable via the SF word loaded to the filter register.
Output data rates vary from 5.35 Hz (186.77 ms) to 105.03 Hz
(9.52 ms). The output data rate
The overall frequency response from the digital filter with chop-
ping enabled is the product of a sinc
3
and a sinc response. There
are sinc
3
notches at integer multiples of 3
×
f
ADC
and there are
sinc notches at odd integer multiples of f
ADC
/2. Normal mode
rejection is the major function of the digital filter on the AD7708/
AD7718. The normal mode 50
±
1 Hz rejection with an SF word
of 82 is typically –100 dB. The 60
±
1 Hz rejection with SF = 68 is
typically –100 dB. Simultaneous 50 Hz and 60 Hz rejection of
better than 60 dB is achieved with an SF of 69 and gives a data
update rate of 19.8 Hz and a channel settling time of 101 ms. The
AD7708/AD7718 are factory-calibrated so field calibration will
only be required if the ADC is operated at temperatures that differ
substantially from the factory-calibration conditions.
f
f
SF
ADC
MOD
×
=
24
.
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