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參數資料
| 型號： | AD7718BRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 8-/10-Channel, Low Voltage, Low Power, ADCs |
| 中文描述： | 10-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO28 |
| 封裝： | PLASTIC, TSSOP-28 |
| 文件頁數： | 12/44頁 |
| 文件大?。?/td> | 339K |
| 代理商： | AD7718BRU |
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REV. 0
–12–
AD7708/AD7718
PIN FUNCTION DESCRIPTIONS
Pin No
Mnemonic
Function
1
AIN7
Analog Input Channel 7. Programmable-gain analog input that can be used as a pseudo-
differential input when used with AINCOM, or as the positive input of a fully-differential input
pair when used with AIN8. (See ADC Control Register section.)
Analog Input Channel 8. Programmable-gain analog input that can be used as a pseudo-
differential input when used with AINCOM, or as the negative input of a fully-differential input
pair when used with AIN7. (See ADC Control Register section.)
Analog Supply Voltage
Analog Ground
Negative Reference Input. This reference input can lie anywhere between AGND and AV
DD
– 1 V.
Positive reference input. REFIN(+) can lie anywhere between AV
DD
and AGND. The nominal
reference voltage [REFIN(+)–REFIN(–)] is 2.5 V but the part is functional with a reference
range from 1 V to AV
DD
.
Analog Input Channel 1. Programmable-gain analog input that can be used as a pseudo-
differential input when used with AINCOM, or as the positive input of a fully-differential input
pair when used with AIN2. (See ADC Control Register Section.)
Analog Input Channel 2. Programmable-gain analog input that can be used as a pseudo-
differential input when used with AINCOM, or as the negative input of a fully-differential input
pair when used with AIN1. (See ADC Control Register section.)
Analog Input Channel 3. Programmable-gain analog input that can be used as a pseudo-
differential input when used with AINCOM, or as the positive input of a fully-differential input
pair when used with AIN4. (See ADC Control Register section.)
Analog Input Channel 4. Programmable-gain analog input that can be used as a pseudo-
differential input when used with AINCOM, or as the negative input of a fully-differential input
pair when used with AIN3. (See ADC Control Register section.)
Analog Input Channel 5. Programmable-gain analog input that can be used as a pseudo-
differential input when used with AINCOM, or as the positive input of a fully-differential input
pair when used with AIN6. (See ADC Control Register section ADCCON.)
All analog inputs are referenced to this input when configured in pseudo-differential input mode.
Positive reference input/analog input. This input can be configured as a reference input with the
same characteristics as REFIN1(+) or as an additional analog input. When configured as an
analog input this pin provides a programmable-gain analog input that can be used as a pseudo-
differential input when used with AINCOM, or as the positive input of a fully-differential input
pair when used with AIN10. (See ADC Control Register section.)
Negative reference input/analog input. This pin can be configured as a reference or analog input.
When configured as a reference input it provides the negative reference input for REFIN2.
When configured as an analog input it provides a programmable-gain analog input that can be
used as a pseudo-differential input when used with AINCOM, or as the negative input of a fully-
differential input pair when used with AIN9. (See ADC Control Register section.)
Analog Input Channel 6. Programmable-gain analog input that can be used as a pseudo-
differential input when used with AINCOM, or as the negative input of a fully-differential input
pair when used with AIN5. (See ADC Control Register section.)
P2 can act as a general-purpose Input/Output bit referenced between AV
DD
and AGND. There
is a weak pull-up to AV
DD
internally on this pin.
It is recommended that this pin be tied directly to AGND.
P1 can act as a general-purpose Input/Output bit referenced between AV
DD
and AGND. There
is a weak pull-up to AV
DD
internally on this pin.
Digital input used to reset the ADC to its power-on-reset status. This pin has a weak pull-up
internally to DV
DD
.
Serial clock input for data transfers to and from the ADC. The SCLK has a Schmitt-trigger
input making an opto-isolated interface more robust. The serial clock can be continuous with all
data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock
with the information being transmitted to or from the AD7708/AD7718 in smaller batches of data.
2
AIN8
3
4
5
6
AV
DD
AGND
REFIN1(–)
REFIN1(+)
7
AIN1
8
AIN2
9
AIN3
10
AIN4
11
AIN5
12
13
AINCOM
REFIN2(+)/AIN9
14
REFIN2(–)/AIN10
15
AIN6
16
P2
17
18
AGND
P1
19
RESET
20
SCLK
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