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參數(shù)資料
| 型號： | AD7721AR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | CMOS 16-Bit, 468.75 kHz, Sigma-Delta ADC |
| 中文描述： | 1-CH 16-BIT DELTA-SIGMA ADC, SERIAL/PARALLEL ACCESS, PDSO28 |
| 封裝： | 0.300 INCH, SOIC-28 |
| 文件頁數(shù)： | 12/16頁 |
| 文件大小： | 259K |
| 代理商： | AD7721AR |
AD7721
REV. A
–12–
PARALLE L INT E RFACE
Read Operation
T he device defaults to parallel mode if
CS
,
RD
and
WR
are not
tied to DGND together. Figure 11 shows a timing diagram for
reading from the AD7721 in the parallel mode. When operating
the device in parallel mode,
CS
and
RD
should be tied to
DGND permanently except when control information is being
written to the AD7721.
DRDY
goes high for 2 clock cycles to
indicate that new data is available from the interface. T he
AD7721 outputs this data after the falling edge of
DRDY
. T his
DRDY
pin can be used to drive an edge-triggered interrupt of a
microprocessor.
Write Operation
T he write operation is used to write data into the control regis-
ter. T he outputs of the control register select the analog input
range, allow the part to be put into power-down (standby)
mode, define the function of the DVAL/
SYNC
pin, and initiate
the calibration routine. After power-up and after at least 16
clock cycles, the control register must be written to. A cali-
bration must also be performed at least once after power-up to
set the calibration registers. T he function of each bit in the
control register is shown in T able I. When writing to the con-
trol register, the
RD
pin must be taken high so that the pins D0
to D11 are configured as inputs.
DATA OUT (O)
SCLK (O)
DB0
DB10
DB11
DB12
DB13
DB14
DB15
RFS
(I) /
DRDY
(O)
t
2
t
3
t
4
t
5
t
6
t
8
NOTE: (I) SIGNIFIES AN INPUT; (O) SIGNIFIES AN OUTPUT.
t
1
t
9
t
7
Figure 10. Serial Mode Output Register Read
DRDY
(O)
DB0–DB11 (O)
RD
(I)
CS
(I)
t
12
t
11
NOTE: (I) SIGNIFIES AN INPUT; (O) SIGNIFIES AN OUTPUT.
t
10
Figure 11. Parallel Mode Output Register Read
NOTE: (I) SIGNIFIES AN INPUT; (O) SIGNIFIES AN OUTPUT.
WR
(I)
VALID DATA
CS
(I)
DB0–DB11 (I)
t
14
t
15
t
13
Figure 12. Write Timing Diagram
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD7721SQ | CMOS 16-Bit, 468.75 kHz, Sigma-Delta ADC |
| AD7722 | 16-Bit, 195 kSPS CMOS, Sigma-Delta ADC |
| AD7722AS | 16-Bit, 195 kSPS CMOS, Sigma-Delta ADC |
| AD7723 | 16-Bit, 1.2 MSPS CMOS, Sigma-Delta ADC |
| AD7723BS | 16-Bit, 1.2 MSPS CMOS, Sigma-Delta ADC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7721AR-REEL | 制造商:Analog Devices 功能描述:ADC Single Delta-Sigma 468.75ksps 16-bit Parallel/Serial 28-Pin SOIC W T/R |
| AD7721ARZ | 功能描述:IC ADC 16BIT SIGMA-DELTA 28SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個(gè)單端，單極；2 個(gè)差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD7721ARZ-REEL | 功能描述:IC ADC 16BIT SIGMA-DELTA 28SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個(gè)單端，單極；1 個(gè)單端，雙極 |
| AD7721SQ | 制造商:AD 制造商全稱:Analog Devices 功能描述:CMOS 16-Bit, 468.75 kHz, Sigma-Delta ADC |
| AD7722 | 制造商:AD 制造商全稱:Analog Devices 功能描述:16-Bit, 195 kSPS CMOS, Sigma-Delta ADC |
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