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參數資料
| 型號： | AD773A |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | ADC |
| 英文描述： | 10-Bit, 20 MSPS Monolithic A/D Converter |
| 中文描述： | 10位，20 MSPS的單片機的A / D轉換器 |
| 文件頁數： | 5/16頁 |
| 文件大?。?/td> | 223K |
| 代理商： | AD773A |
AD773A
REV. 0
–5–
INT E GRAL NONLINE ARIT Y (INL)
Linearity error refers to the deviation of each individual code
from a line drawn from “zero” through “full scale.” T he point
used as “zero” occurs 1/2 LSB before the first code transition.
“Full scale” is defined as a level 1 1/2 LSB beyond the last code
transition. T he deviation is measured from the center of each
particular code to the true straight line.
DIFFE RE NT IAL LINE ARIT Y E RROR
(DNL, NO MISSING CODE S)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value.
ZE RO E RROR
T he major carry transition should occur for an analog value
1/2 LSB below analog common. Zero error is defined as the
deviation of the actual transition from that point.
GAIN E RROR
T he first code transition should occur for an analog value
1/2 LSB above nominal negative full scale. T he last transition
should occur 1 1/2 LSB below the nominal positive full scale.
Gain error is the deviation of the actual difference between first
and last code transitions and the ideal difference between first
and last code transitions.
POWE R SUPPLY RE JE CT ION
One of the effects of power supply variation on the performance
of the device will be a change in gain error. T he specification
shows the maximum gain error deviation as the supplies are
varied from their nominal values to their specified limits.
SIGNAL-T O-NOISE PLUS DIST ORT ION (S/N+D) RAT IO
S/N+D is the ratio of the rms value of the measured input signal
to the rms sum of all other spectral components including
harmonics but excluding dc. T he value for S/N+D is expressed
in decibels.
E FFE CT IVE NUMBE R OF BIT S (E NOB)
ENOB is calculated from the following expression:
S/N+D = 6.02N + 1.76, where N is equal to the effective
number of bits.
T OT AL HARMONIC DIST ORT ION (T HD)
T HD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured input signal and is
expressed as a percentage or in decibels.
SPURIOUS FRE E DY NAMIC RANGE
T he peak spurious or peak harmonic component is the largest
spectral component excluding the input signal and dc. T his
value is expressed in decibels relative to the rms value of a full-
scale input signal.
INT E RMODULAT ION DIST ORT ION (IMD)
With inputs consisting of sine waves at two frequencies, fa and
fb, any device with nonlinearities will create distortion products,
of order (m+n), at sum and difference frequencies of mfa
±
nfb,
where m, n = 0, 1, 2, 3. . . . Intermodulation terms are those for
which m or n is not equal to zero. For example, the second
order terms are (fa+fb) and (fa–fb) and the third order terms are
(2fa+fb), (2fa–fb), (fa+2fb) and (fa–2fb). T he IMD products
are expressed as the decibel ratio of the rms sum of the
measured input signals to the rms sum of the distortion terms.
T he two signals are of equal amplitude and the peak value of
their sums is –0.5 dB from full scale. T he IMD products are
normalized to a 0 dB input signal.
DIFFE RE NT IAL GAIN
T he percentage difference between the output amplitudes of a
small high frequency sine wave at two stated levels of a low
frequency signal on which it is superimposed.
DIFFE RE NT IAL PHASE
T he difference in the output phase of a small high frequency
sine wave at two stated levels of a low frequency signal on which
it is superimposed.
T RANSIE NT RE SPONSE
T he time required for the AD773A to achieve its rated accuracy
after a full-scale step function is applied to its input.
OVE RVOLT AGE RE COVE RY T IME
T he time required for the ADC to recover to full accuracy after
an analog input signal 150% of full scale is reduced to 50% of
the full-scale value.
APE RT URE DE LAY
T he difference between the switch delay and the analog delay of
the T HA. T his effective delay represents the point in time,
relative to the falling edge of the CLOCK input, that the analog
input is sampled.
APE RT URE JIT T E R
T he variations in aperture delay for successive samples.
PIPE LINE DE LAY (LAT E NCY )
T he number of clock cycles between conversion initiation and
the associated output data being made available. New output
data is provided every clock cycle.
FULL POWE R BANDWIDT H
T he input frequency at which the amplitude of the reconstructed
fundamental is reduced by 3 dB for a full-scale input.
Definitions of Specifications–
相關PDF資料 |
PDF描述 |
|---|---|
| AD773AJD | 10-Bit, 20 MSPS Monolithic A/D Converter |
| AD773AKD | 10-Bit, 20 MSPS Monolithic A/D Converter |
| AD7740KRM | 3 V/5 V Low Power, Synchronous Voltage-to-Frequency Converter |
| AD7740YRT | 3 V/5 V Low Power, Synchronous Voltage-to-Frequency Converter |
| AD7740 | 3 V/5 V Low Power, Synchronous Voltage-to-Frequency Converter |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD773AJD | 制造商:Analog Devices 功能描述:ADC Single Pipelined 20Msps 10-bit Parallel 28-Pin CDIP 制造商:Rochester Electronics LLC 功能描述:IC, 10-BIT 20 MSPS ADC - Bulk |
| AD773AKD | 制造商:AD 制造商全稱:Analog Devices 功能描述:10-Bit, 20 MSPS Monolithic A/D Converter |
| AD773ASD/883B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog-to-Digital Converter， 10-Bit |
| AD773-EB | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD773JD | 制造商:Analog Devices 功能描述: |
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