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參數(shù)資料
| 型號： | AD7788ARM |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Low Power, 16-/24-Bit Sigma-Delta ADC |
| 中文描述： | 1-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO10 |
| 封裝： | MO-187BA, MSOP-10 |
| 文件頁數(shù)： | 6/20頁 |
| 文件大小： | 288K |
| 代理商： | AD7788ARM |
AD7788/AD7789
TIMING CHARACTERISTICS
1, 2
Table 4. (V
DD
= 2.5 V to 5.25 V (AD7788B and AD7789), V
DD
= 2.7 V to 5.25 V (AD7788A); GND = 0 V, REFIN(+) = 2.5 V,
REFIN(–) = GND, Input Logic 0 = 0 V, Input Logic 1 = V
DD
, unless otherwise noted.)
Limit at T
MIN
, T
MAX
(B Version)
Unit
t
3
100
ns min
t
4
100
ns min
Read Operation
t
1
0
ns min
60
ns max
80
ns max
t
23
0
ns min
60
ns max
80
ns max
t
55, 6
10
ns min
80
ns max
t
6
100
ns max
t
7
10
ns min
Write Operation
t
8
0
ns min
t
9
30
ns min
t
10
25
ns min
t
11
0
ns min
Rev. 0 | Page 6 of 20
Parameter
Conditions/Comments
SCLK High Pulsewidth
SCLK Low Pulsewidth
CS Falling Edge to DOUT/RDY Active Time
V
DD
= 4.75 V to 5.25 V
V
DD
= 2.7 V to 3.6 V
SCLK Active Edge to Data Valid Delay
4
V
DD
= 4.75 V to 5.25 V
V
DD
= 2.7 V to 3.6 V
Bus Relinquish Time after CS Inactive Edge
SCLK Inactive Edge to CS Inactive Edge
SCLK Inactive Edge to DOUT/RDY High
CS Falling Edge to SCLK Active Edge Setup Time
4
Data Valid to SCLK Edge Setup Time
Data Valid to SCLK Edge Hold Time
CS Rising Edge to SCLK Edge Hold Time
1
Sample tested during initial release to ensure compliance. All input signals are specified with t
R
= t
F
= 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
2
See Figure 3 and Figure 4.
3
These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the V
OL
or V
OH
limits.
4
SCLK active edge is falling edge of SCLK.
5
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and, as such, are independent of external bus loading capacitances.
6
RDY returns high after a read of the ADC. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY is high,
although care should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read
only once.
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| AD7788BRM-REEL | 制造商:Analog Devices 功能描述:ADC Single Delta-Sigma 16.6sps 16-bit Serial 10-Pin MSOP T/R 制造商:Analog Devices 功能描述:ADC SGL DELTA-SIGMA 0.0166KSPS 16BIT SERL 10MSOP - Tape and Reel |
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