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參數(shù)資料
| 型號： | AD7822BRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 3 V/5 V, 2 MSPS, 8-Bit, 1-, 4-, 8-Channel Sampling ADCs |
| 中文描述： | 1-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDSO20 |
| 封裝： | MO-153AC, TSSOP-20 |
| 文件頁數(shù)： | 5/18頁 |
| 文件大小： | 215K |
| 代理商： | AD7822BRU |
AD7822/AD7825/AD7829
–5–
REV. A
PIN FUNCTION DESCRIPTIONS
Mnemonic
Description
V
IN1
to V
IN8
Analog Input Channels. The AD7822 has a single input channel; the AD7825 and AD7829 have four and eight
analog input channels respectively. The inputs have an input span of 2.5 V and 2 V depending on the sup-
ply voltage (V
DD
). This span may be centered anywhere in the range AGND to V
DD
using the V
MID
Pin. The
default input range (V
MID
unconnected) is AGND to 2 V (V
DD
= 3 V
±
10%) or AGND to 2.5 V (V
DD
= 5 V
±
10%). See Analog Input section of the data sheet for more information.
Positive supply voltage, 3 V
±
10% and 5 V
±
10%.
Analog Ground. Ground reference for track/hold, comparators, reference circuit and multiplexer.
Digital Ground. Ground reference for digital circuitry.
Logic Input Signal. The convert start signal initiates an 8-bit analog-to-digital conversion on the falling edge of
this signal. The falling edge of this signal places the track/hold in hold mode. The track/hold goes into track
mode again 120 ns after the start of a conversion. The state of the
CONVST
signal is checked at the end of
a conversion. If it is logic low, the AD7822/AD7825/AD7829 will power down. (See Operating Mode section of
the data sheet.)
Logic Output. The End of Conversion signal indicates when a conversion has finished. The signal can be used
to interrupt a microcontroller when a conversion has finished or latch data into a gate array. (See Parallel Inter-
face section of this data sheet.)
Logic input signal. The chip select signal is used to enable the parallel port of the AD7822, AD7825, and AD7829.
This is necessary if the ADC is sharing a common data bus with another device.
Logic Input. The Power-Down pin is present on the AD7822 and AD7825 only. Bringing the
PD
pin low
places the AD7822 and AD7825 in Power-Down mode. The ADCs will power-up when
PD
is brought logic
high again.
Logic Input Signal. The read signal is used to take the output buffers out of their high impedance state and
drive data onto the data bus. The signal is internally gated with the
CS
signal. Both
RD
and
CS
must be logic
low to enable the data bus.
Channel Address Inputs. The address of the next multiplexer channel must be present on these inputs when the
RD
signal goes low.
Data Output Lines. They are normally held in a high impedance state. Data is driven onto the data bus when
both
RD
and
CS
go active low.
Analog Input and Output. An external reference can be connected to the AD7822, AD7825, and AD7829 at this
pin. The on-chip reference is also available at this pin.
V
DD
AGND
DGND
CONVST
EOC
CS
PD
RD
A0–A2
DB0–DB7
V
REF IN
/
OUT
PIN CONFIGURATIONS
DIP/SOIC/TSSOP
14
13
12
11
17
16
15
20
19
18
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
AD7822
NC = NO CONNECT
DB2
DB6
DB5
DB4
DB3
DB1
DB0
CONVST
V
DD
AGND
DB7
CS
RD
DGND
EOC
PD
NC
V
IN1
V
MID
V
REF
13
16
15
14
24
23
22
21
20
19
18
17
TOP VIEW
(Not to Scale)
12
11
10
9
8
1
2
3
4
7
6
5
AD7825
DB2
DB6
DB5
DB4
DB3
DB1
DB0
CONVST
V
DD
V
REF
AGND
DB7
CS
RD
DGND
EOC
A1
A0
V
IN1
V
IN2
V
IN3
V
MID
PD
V
IN4
14
13
12
11
17
16
15
20
19
18
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
28
27
26
25
24
23
22
21
AD7829
DB2
DB6
DB5
DB4
DB3
DB1
DB0
CONVST
V
DD
V
REF
AGND
DB7
CS
RD
DGND
EOC
A2
A1
V
IN1
V
IN2
V
IN3
V
MID
A0
V
IN8
V
IN7
V
IN6
V
IN5
V
IN4
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