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參數資料
| 型號： | AD7827 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 3 V/5 V, 1 MSPS, 8-Bit, Serial Interface Sampling ADC |
| 中文描述： | 3伏/ 5伏，1 MSPS的，8位，串行接口采樣ADC |
| 文件頁數： | 5/12頁 |
| 文件大小： | 185K |
| 代理商： | AD7827 |
AD7827
–5–
REV. 0
T E RMINOLOGY
Signal-to-(Noise + Distortion) Ratio
T his is the measured ratio of signal-to-(noise + distortion) at
the output of the A/D converter. T he signal is the rms amplitude
of the fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (f
S
/2), excluding dc.
T he ratio is dependent upon the number of quantization levels in
the digitization process; the more levels, the smaller the quantiza-
tion noise. T he theoretical signal-to-(noise + distortion) ratio for
an ideal N-bit converter with a sine wave input is given by:
Signal-to-
(
Noise
+
Distortion
) = (6.02
N
+ 1.76)
dB
T hus for an 8-bit converter, this is 50 dB.
T otal Harmonic Distortion
T otal harmonic distortion (T HD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7827 it is defined as:
THD
(
dB
)
=
20 log
V
2
2
+
V
3
2
+
V
4
V
1
2
+
V
5
2
+
V
6
2
where
V
1
is the rms amplitude of the fundamental and
V
2
,
V
3
,
V
4
,
V
5
and
V
6
are the rms amplitudes of the second through the sixth
harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to f
S
/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is deter-
mined by the largest harmonic in the spectrum, but for parts
where the harmonics are buried in the noise floor, it will be a
noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa
±
nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for
which neither m nor n are equal to zero. For example, the sec-
ond order terms include (fa + fb) and (fa – fb), while the third
order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).
T he AD7827 is tested using the CCIF standard where two
input frequencies near the top end of the input bandwidth are
used. In this case, the second and third order terms are of dif-
ferent significance. T he second order terms are usually dis-
tanced in frequency from the original sine waves while the third
order terms are usually at a frequency close to the input fre-
quencies. As a result, the second and third order terms are
specified separately. T he calculation of the intermodulation
distortion is as per the T HD specification where it is the ratio
of the rms sum of the individual distortion products to the rms
amplitude of the fundamental expressed in dBs.
Relative Accuracy
Relative accuracy or endpoint nonlinearity is the maximum
deviation from a straight line passing through the endpoints of
the ADC transfer function.
Differential Nonlinearity
T his is the difference between the measured and the ideal
1 LSB change between any two adjacent codes in the ADC.
Offset E rror
T his is the deviation of the 128th code transition (01111111) to
(10000000) from the ideal, i.e., V
REF
/2 (V
DD
= 5 V), 0.8 V
REF
/2
(V
DD
= 3 V).
Zero Scale E rror
T his is the deviation of the first code transition (00000000) to
(00000001) from the ideal, i.e., V
REF
/2 –1.25 V + 1 LSB (V
DD
=
5 V
±
10%), or 0.8 V
REF
/2 –1.0 V + 1 LSB (V
DD
= 3 V
±
10%).
Full-Scale E rror
T his is the deviation of the last code transition (11111110) to
(11111111) from the ideal, i.e., V
MID
+ 1.25 V – 1 LSB (V
DD
=
5 V
±
10%), or V
MID
+ 1.0 V – 1 LSB (V
DD
= 3 V
±
10%).
Gain E rror
T his is the deviation of the last code transition (1111 . . . 110) to
(1111 . . . 111) from the ideal, i.e., V
REF
– 1 LSB, after the offset
error has been adjusted out.
T rack/Hold Acquisition T ime
T rack/hold acquisition time is the time required for the output
of the track/hold amplifier to reach its final value, within
±
1/2 LSB, after the point at which the track/hold returns to
track mode. T his happens approximately 120 ns after the falling
edge of
CONVST
.
It also applies when there is a step input change on the input
voltage applied to the V
IN
input of the AD7827. It means that
the user must wait for the duration of the track/hold acquisition
time after the end of conversion or after a step input change to
V
IN
before starting another conversion, to ensure that the part
operates to specification.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD7827BN | 制造商:Analog Devices 功能描述:ADC Single Semiflash 1Msps 8-bit Serial 8-Pin PDIP 制造商:Rochester Electronics LLC 功能描述:8-BIT SERIAL 2MSPS ADC - Bulk 制造商:Analog Devices 功能描述:IC 8BIT ADC 7827 DIP8 |
| AD7827BNZ | 制造商:Analog Devices 功能描述:ADC Single Semiflash 1Msps 8-bit Serial 8-Pin PDIP 制造商:Analog Devices 功能描述:IC 8BIT ADC 7827 DIP8 |
| AD7827BR | 制造商:Analog Devices 功能描述:ADC Single Semiflash 1Msps 8-bit Serial 8-Pin SOIC N 制造商:Rochester Electronics LLC 功能描述:8-BIT SERIAL 2MSPS ADC - Bulk |
| AD7827BR-REEL | 制造商:Analog Devices 功能描述:ADC Single Semiflash 1Msps 8-bit Serial 8-Pin SOIC N T/R 制造商:Rochester Electronics LLC 功能描述:8-BIT SERIAL 2MSPS ADC - Tape and Reel |
| AD7827BR-REEL7 | 制造商:Analog Devices 功能描述:ADC Single Semiflash 1Msps 8-bit Serial 8-Pin SOIC N T/R 制造商:Rochester Electronics LLC 功能描述:8-BIT SERIAL 2MSPS ADC - Tape and Reel |
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