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參數(shù)資料
| 型號： | AD7828LP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | LC2MOS High Speed 4- & 8-Channel 8-Bit ADCs |
| 中文描述： | 8-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PQCC28 |
| 封裝： | PLASTIC, MO-047AB, LCC-28 |
| 文件頁數(shù)： | 3/16頁 |
| 文件大小： | 270K |
| 代理商： | AD7828LP |
AD7824/AD7828
REV. F
–3–
TIMING CHARACTERISTICS
1
(V
DD
= 5 V; V
REF
(+) = 5 V; V
REF
(–) = GND = 0 V, unless otherwise noted.)
Limit at 25 C
Limit at T
MIN
, T
MAX
Parameter
(All Grades)
(K, L, B, C Grades)
Limit at T
MIN
, T
MAX
(T, U Grades)
Unit
Conditions/Comments
t
CSS
t
CSH
t
AS
t
AH
t
RDY2
0
0
0
30
40
0
0
0
35
60
0
0
0
40
60
ns min
ns min
ns min
ns min
ns max
CS
to
RD
Setup Time
CS
to
RD
Hold Time
Multiplexer Address Setup Time
Multiplexer Address Hold Time
CS
to RDY Delay. Pull-Up
Resistor 5 k
.
Conversion Time, Mode 0
Data Access Time after
RD
Data Access Time after
INT
, Mode 0
RD
to
INT
Delay
t
CRD
t
ACC13
t
ACC23
t
lNTH2
2.0
85
50
40
75
60
500
60
600
2.4
110
60
65
100
70
500
80
500
2.8
120
70
70
100
70
600
80
400
μ
s max
ns max
ns max
ns typ
ns max
ns max
ns min
ns min
ns max
t
DH4
t
P
t
RD
Data Hold Time
Delay Time between Conversions
Read Pulsewidth, Mode 1
NOTES
1
Sample tested at 25
°
C to ensure compliance. All input control signals are specified with t
RISE
= t
FALL
= 20 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
C
L
= 50 pF.
3
Measured with load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
4
Defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 2.
Specifications subject to change without notice.
Test Circuits
DBN
3k
100pF
DGND
a. High-Z to V
OH
DBN
3k
100pF
DGND
5V
b. High-Z to V
OL
Figure 1. Load Circuits for Data Access Time Test
DBN
3k
10pF
DGND
a. V
OH
to High-Z
DBN
3k
10pF
DGND
5V
b. V
OL
to High-Z
Figure 2. Load Circuits for Data Hold Time Test
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