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參數資料
| 型號： | AD7837AR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | LC2MOS Complete, Dual 12-Bit MDACs |
| 中文描述： | DUAL, PARALLEL, WORD INPUT LOADING, 3 us SETTLING TIME, 12-BIT DAC, PDSO24 |
| 封裝： | SOIC-24 |
| 文件頁數： | 8/12頁 |
| 文件大小： | 187K |
| 代理商： | AD7837AR |
AD7837/AD7847
REV. C
–8–
DATA
t
6
t
3
t
8
WR
DATA
ADDRESS DATA
t
7
t
1
t
2
t
5
t
4
CS
A0/A1
LDAC
Figure 14. AD7837 Write Cycle Timing Diagram
CS
,
WR
, A0 and A1 control the loading of data to the input
latches. The eight data inputs accept right-justified data. Data
can be loaded to the input latches in any sequence. Provided that
LDAC
is held high, there is no analog output change as a result
of loading data to the input latches. Address lines A0 and A1
determine which latch data is loaded to when
CS
and
WR
are low.
The control logic truth table for the part is shown in Table II.
Table II. AD7837 Truth Table
CS WR
A1 A0
LDAC
Function
1
X
0
0
0
0
1
X
1
0
0
0
0
1
X
X
0
0
1
1
X
X
X
0
1
0
1
X
1
1
1
1
1
1
0
No Data Transfer
No Data Transfer
DAC A LS Input Latch Transparent
DAC A MS Input Latch Transparent
DAC B LS Input Latch Transparent
DAC B MS Input Latch Transparent
DAC A and DAC B DAC Latches
Updated Simultaneously from the
Respective Input Latches
X = Don’t Care.
The
LDAC
input controls the transfer of 12-bit data from the
input latches to the DAC latches. When
LDAC
is taken low, both
DAC latches, and hence both analog outputs, are updated at
the same time. The data in the DAC latches is held on the rising
edge of
LDAC
. The
LDAC
input is asynchronous and indepen-
dent of
WR
. This is useful in many applications especially in the
simultaneous updating of multiple AD7837s. However, care must
be taken while exercising
LDAC
during a write cycle. If an
LDAC
operation overlaps a
CS
and
WR
operation, there is a possibility
of invalid data being latched to the output. To avoid this,
LDAC
must remain low after
CS
or
WR
return high for a period equal
to or greater than t
8
, the minimum
LDAC
pulsewidth.
UNIPOLAR BINARY OPERATION
Figure 15 shows DAC A on the AD7837/AD7847 connected
for unipolar binary operation. Similar connections apply for
DAC B. When V
IN
is an ac signal, the circuit performs 2-quad-
rant multiplication. The code table for this circuit is shown in
Table III. Note that on the AD7847 the feedback resistor R
FB
is
internally connected to V
OUT
.
DAC A
AGNDA
V
OUTA
V
REFA
V
IN
DGND
V
SS
R
FBA
*
V
SS
V
DD
V
DD
AD7837
AD7847
V
OUT
*
INTERNALLY
CONNECTED
ON AD7847
Figure 15. Unipolar Binary Operation
Table III. Unipolar Code Table
DAC Latch Contents
MSB LSB
Analog Output, V
OUT
1111 1111 1111
–
V
IN
×
4095
4096
1000 0000 0000
–
V
IN
×
2048
4096
=
–
1/2
V
IN
0000 0000 0001
0 V
–
V
IN
×
1
4096
0000 0000 0000
Note 1 LSB =
V
IN
4096
.
相關PDF資料 |
PDF描述 |
|---|---|
| AD7837BN | LC2MOS Complete, Dual 12-Bit MDACs |
| AD7837BQ | 2.7V-5.25V Digital, 5V Analog, 14 Bit, 1.25 MSPS, Serial ADC w/Ref 48-TQFP -40 to 85 |
| AD7837BR | LC2MOS Complete, Dual 12-Bit MDACs |
| AD7837SQ | 2.7V-5.25V Digital, 5V Analog, 14 Bit, 1.25 MSPS, Serial ADC w/Ref 48-TQFP -40 to 85 |
| AD7847 | LC2MOS Complete, Dual 12-Bit MDACs |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD7837AR/883B | 制造商:AD 制造商全稱:Analog Devices 功能描述:LC2MOS Complete, Dual 12-Bit MDACs |
| AD7837AR883B | 制造商:AD 制造商全稱:Analog Devices 功能描述:LC2MOS Complete, Dual 12-Bit MDACs |
| AD7837AR-883B | 制造商:AD 制造商全稱:Analog Devices 功能描述:LC2MOS Complete, Dual 12-Bit MDACs |
| AD7837ARN | 制造商:AD 制造商全稱:Analog Devices 功能描述:LC2MOS Complete, Dual 12-Bit MDACs |
| AD7837ARQ | 制造商:AD 制造商全稱:Analog Devices 功能描述:LC2MOS Complete, Dual 12-Bit MDACs |
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