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| 型號(hào)： | AD783 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | Complete Very High Speed Sample-and-Hold Amplifier(高速采樣保持放大器) |
| 中文描述： | 完整的超高速采樣保持放大器（高速采樣保持放大器） |
| 文件頁數(shù)： | 1/8頁 |
| 文件大小： | 138K |
| 代理商： | AD783 |
FUNCT IONAL BLOCK DIAGRAM
1
2
3
4
5
6
7
8
AD783
V
CC
IN
COMMON
NC
OUT
S/H
NC
V
EE
NC = NO CONNECT
X1
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
Complete Very Hgh Speed
Sample-and-Hold Amplifier
AD783*
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
FEATURES
Acquisition Time to 0.01%: 250 ns Typical
Low Power Dissipation: 95 mW
Low Droop Rate: 0.02
m
V/
m
s
Fully Specified and Tested Hold Mode Distortion
Total Harmonic Distortion: –85 dB
Aperture J itter: 50 ps Maximum
Internal Hold Capacitor
Self-Correcting Architecture
8-Pin Mini Cerdip and SOIC Packages
PRODUCT DE SCRIPT ION
T he AD783 is a high speed, monolithic sample-and-hold
amplifier (SHA). T he AD783 offers a typical acquisition time
of 250 ns to 0.01%. T he AD783 is specified and tested for hold
mode total harmonic distortion with input frequencies up to
100 kHz. T he AD783 is configured as a unity gain amplifier
and uses a patented self-correcting architecture that minimizes
hold mode errors and ensures accuracy over temperature. T he
AD783 is self-contained and requires no external components
or adjustments.
T he AD783 retains the held value with a droop rate of 0.02
μ
V/
μ
s. Excellent linearity and hold mode dc and dynamic perfor-
mance make the AD783 ideal for high speed 12- and 14-bit
analog-to-digital converters.
T he AD783 is manufactured on Analog Devices’ ABCMOS
process which merges high performance, low noise bipolar
circuitry with low power CMOS to provide an accurate, high
speed, low power SHA.
T he J grade device is specified for operation from 0
°
C to +70
°
C
and the A grade from –40
°
C to +85
°
C. T he J and A grades are
available in 8-pin cerdip and SOIC packages. T he military
temperature range version is specified for operation from –55
°
C
to +125
°
C and is available in an 8-pin cerdip package. For
details refer to the
Analog Devices Military Products Databook
or
AD783/883B data sheet.
*
Protected by U.S. Patent Number 4,962,325.
PRODUCT HIGHLIGHT S
1. Fast acquisition time (250 ns), low aperture jitter (20 ps) and
fully specified hold mode distortion make the AD783 an
ideal SHA for sampling systems.
2. Low droop (0.02
μ
V/
μ
s) and internally compensated hold
mode error result in superior system accuracy.
3. Low power (95 mW typical), complete functionality and
small size make the AD783 an ideal choice for a variety of
high performance applications.
4. T he AD783 requires no external components or adjustments.
5. T he AD783 is an excellent choice as a front-end SHA for
high speed analog-to-digital converters such as the AD671,
AD7586, AD674B, AD774B, AD7572 and AD7672.
6. Fully specified and tested hold mode distortion guarantees
the performance of the SHA in sampled data systems.
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