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參數資料
| 型號： | AD7840 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | LC2MOS Complete 14-Bit DAC |
| 中文描述： | LC2MOS完整的14位DAC |
| 文件頁數： | 11/16頁 |
| 文件大小： | 337K |
| 代理商： | AD7840 |
AD7840
REV. B
–11–
AD7840–68000 Interface
An interface between the AD7840 and the 68000 microproces-
sor is shown in Figure 19. In this interface example, the
LDAC
input is hardwired low. As a result the DAC latch and analog
output are updated on the rising edge of
WR
. A single move
instruction, therefore, loads the input latch and updates the output.
MOVE.W D0,$DAC
D0 = 68000 D0 Register
DAC = AD7840 Address
Figure 19. AD7840–MC68000 Parallel Interface
Serial Interfacing
Figures 20 to 23 show the AD7840 configured for serial inter-
facing with the
CS
input hardwired to –5 V. T he parallel bus is
not activated during serial communication with the AD7840.
AD7840–ADSP-2101/ADSP-2102 Serial Interface
Figure 20 shows a serial interface between the AD7840 and the
ADSP-2101/ADSP-2102 DSP processor. Also included in the
interface is the AD7870, a 12-bit A/D converter. An interface
such as this is suitable for modem and other applications which
have a DAC and an ADC in serial communication with a
microprocessor.
T he interface uses just one of the two serial ports of the
ADSP-2101/ADSP-2102. Conversion is initiated on the
AD7870 at a fixed sample rate (e.g., 9.6 kHz) which is provided
by a timer or clock recovery circuitry. While communication
takes place between the ADC and the ADSP-2101/ ADSP-2102,
the AD7870
SSTRB
line is low. T his
SSTRB
line is used to
provide a frame synchronization pulse for the AD7840
SYNC
and ADSP-2101/ADSP-2102 T FS lines. T his means that com-
munication between the processor and the AD7840 can only
take place while the AD7870 is communicating with the processor.
T his arrangement is desirable in systems such as modems where
the DAC and ADC communication should be synchronous.
T he use of the AD7870 SCLK for the AD7840 SCLK and
ADSP-2101/ADSP-2102 SCLK means that only one serial port
of the processor is used. T he serial clock for the AD7870 must
be set for continuous clock for correct operation of this interface.
Data from the ADSP-2101/ADSP-2102 is valid on the falling
edge of SCLK . T he
LDAC
input of the AD7840 is permanently
low so the update of the DAC latch and analog output takes
place on the sixteenth falling edge of SCLK (with
SYNC
low).
T he FORMAT pin of the AD7840 must be tied to +5 V and
the JUST IFY pin tied to DGND for this interface to operate
correctly.
Figure 20. Complete DAC/ADC Serial Interface
AD7840–DSP56000 Serial Interface
A serial interface between the AD7840 and the DSP56000 is
shown in Figure 21. T he DSP56000 is configured for normal
mode synchronous operation with gated clock. It is also set up
for a 16-bit word with SCK and SC2 as outputs and the FSL
control bit set to a 0. SCK is internally generated on the
DSP56000 and applied to the AD7840 SCLK input. Data from
the DSP56000 is valid on the falling edge of SCK . T he SC2
output provides the framing pulse for valid data. T his line must
be inverted before being applied to the
SYNC
input of the
AD7840.
T he
LDAC
input of the AD7840 is connected to DGND so the
update of the DAC latch takes place on the sixteenth falling
edge of SCLK . As with the previous interface, the FORMAT
pin of the AD7840 must be tied to +5 V and the JUST IFY pin
tied to DGND.
Figure 21. AD7840–DSP56000 Serial Interface
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