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參數(shù)資料
| 型號： | AD7840JP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | LC2MOS Complete 14-Bit DAC |
| 中文描述： | SERIAL, PARALLEL, WORD INPUT LOADING, 2.5 us SETTLING TIME, 14-BIT DAC, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 4/16頁 |
| 文件大小： | 337K |
| 代理商： | AD7840JP |
AD7840
REV. B
–4–
PIN FUNCT ION DE SCRIPT ION
DIP
Pin
No.
Pin
Mnemonic
Function
1
CS
/SERIAL
Chip Select/Serial Input. When driven with normal logic levels, it is an active low logic input which is used
in conjunction with
WR
to load parallel data to the input latch. For applications where
CS
is perma-
nently low, an R, C is required for correct power-up (see
LDAC
input). If this input is tied to V
SS
, it de-
fines the AD7840 for serial mode operation.
Write/Frame Synchronization Input. In the parallel data mode, it is used in conjunction with
CS
to load
parallel data. In the serial mode of operation, this pin functions as a Frame Synchronization pulse with se-
rial data expected after the falling edge of this signal.
Data Bit 13(MSB)/Serial Data. When parallel data is selected, this pin is the D13 input. In serial mode,
SDAT A is the serial data input which is used in conjunction with
SYNC
and SCLK to transfer serial data
to the AD7840 input latch.
Data Bit 12/Serial Clock. When parallel data is selected, this pin is the D12 input. In the serial mode, it is
the serial clock input. Serial data bits are latched on the falling edge of SCLK when
SYNC
is low.
Data Bit 11/Data Format. When parallel data is selected, this pin is the D11 input. In serial mode, a Logic
1 on this input indicates that the MSB is the first valid bit in the serial data stream. A Logic 0 indicates
that the LSB is the first valid bit (see T able I).
Data Bit 10/Data Justification. When parallel data is selected, this pin is the D10 input. In serial mode,
this input controls the serial data justification (see T able I).
Data Bit 9 to Data Bit 5. Parallel data inputs.
Digital Ground. Ground reference for digital circuitry.
Data Bit 4 to Data Bit 1. Parallel data inputs.
Data Bit 0 (LSB). Parallel data input.
Positive Supply, +5 V
±
5%.
Analog Ground. Ground reference for DAC, reference and output buffer amplifier.
Analog Output Voltage. T his is the buffer amplifier output voltage. Bipolar output range (
±
3 V with REF
IN = +3 V).
Negative Supply Voltage, –5 V
±
5%.
Voltage Reference Output. T he internal 3 V analog reference is provided at this pin. T o operate the
AD7840 with internal reference, REF OUT should be connected to REF IN. T he external load capability
of the reference is 500
μ
A.
Voltage Reference Input. T he reference voltage for the DAC is applied to this pin. It is internally buffered
before being applied to the DAC. T he nominal reference voltage for correct operation of the AD7840 is
3 V.
Load DAC. Logic Input. A new word is loaded into the DAC latch from the input latch on the falling
edge of this signal (see Interface Logic Information section). T he AD7840 should be powered-up with
LDAC
high. For applications where
LDAC
is permanently low, an R, C is required for correct power-up
(see Figure 19).
2
WR/SYNC
3
D13/SDAT A
4
D12/SCLK
5
D11/FORMAT
6
D10/JUST IFY
7–11
12
13–16
17
18
19
20
D9–D5
DGND
D4–D1
D0
V
DD
AGND
V
OUT
21
22
V
SS
REF OUT
23
REF IN
24
LDAC
T able I. Serial Data Modes
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