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參數資料
| 型號： | AD7843 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Touch Screen Digitizer |
| 中文描述： | 觸摸屏數字轉換器 |
| 文件頁數： | 13/16頁 |
| 文件大小： | 193K |
| 代理商： | AD7843 |
REV. 0
AD7843
–13–
Detailed Serial Interface Timing
Figure 10 shows the detailed timing diagram for serial interfacing
to the AD7843. Writing of information to the Control Register
takes place on the first eight rising edges of DCLK in a data
transfer. The Control Register is only written to if a START bit
is detected (see Control Register section) on DIN and the initia-
tion of the following conversion is also dependent on the presence
of the START bit. Throughout the eight DCLK cycles when
data is being written to the part, the DOUT line will be driven
low. The MSB of the conversion result is clocked out on the
falling edge of the ninth DCLK cycle and is valid on the rising
edge of the tenth DCLK cycle, therefore nine leading zeros may
be clocked out prior to the MSB. This means the data seen on
the DOUT line in the twenty four DCLK conversion cycle, will
be presented in the form of nine leading zeros, twelve bits of
data and three trailing zeros.
The rising edge of
CS
will put the bus and the BUSY output
back into three-state, the DIN line will be ignored and if a con-
version is in progress at the time then this will also be aborted.
However, if
CS
is not brought high after the completion of the
conversion cycle, then the part will wait for the next START bit
to initiate the next conversion. This means each conversion
need not necessarily be framed by
CS
, as once
CS
goes low the
part will detect each START bit and clock in the control word
after it on DIN. When the AD7843 is in the 12-bit conversion
mode, a second START bit will not be detected until seven DCLK
pulses have elapsed after a control word has been clocked in on
DIN, i.e., another START bit can be clocked in on the eighth
DCLK rising edge after a control word has been written to the
device (see Fifteen Clock Cycle section). If the device is in the
8-bit conversion mode, a second START bit will not be recog-
nized until three DCLK pulses have elapsed after the control
word has been clocked in, i.e., another START bit can be
clocked in on the fourth DCLK rising edge after a control word
has been written to the device.
Because a START bit can be recognized during a conversion, it
means the control word for the next conversion can be clocked
in during the current conversion, enabling the AD7843 to com-
plete a conversion cycle in less than twenty-four DCLKs.
CS
DCLK
1
8
DOUT
DIN
THREE-STATE
t
ACQ
8
1
8
1
A2
A1
A0
MODESER/
PD1 PD0
S
BUSY
AQUIRE
IDLE
10
9
8
11
THREE-STATE
7
6
5
4
3
2
1
0
CONVERSION
IDLE
(MSB)
(START)
ON
OFF
OFF
(LSB)
ZERO FILLED
ON
OFF
OFF
THREE-STATE
THREE-STATE
X/Y SWITCHES(1)
(SER/
DFR
HIGH)
X/Y SWITCHES(1,2)
(SER/
DFR
LOW)
NOTES
1
Y DRIVERS ARE ON WHEN X IS SELECTED INPUT CHANNEL (A2
–
A0 = 001), X DRIVERS ARE ON WHEN Y IS SELECTED INPUT CHANNEL (A2
–
A0 = 101).
WHEN PD1, PD0 = 10 OR 00, Y
–
WILL TURN ON AT END OF CONVERSION.
2
DRIVERS WILL REMAIN ON IF POWER-DOWN MODE IS 11 (NO POWER-DOWN) UNTIL SELECTED INPUT CHANNEL, REFERENCE MODE,
OR POWER-DOWN MODE IS CHANGED.
Figure 9. Conversion Timing, 24 DCLKS per Conversion Cycle, 8-Bit Bus Interface. No DCLK delay required with dedi-
cated serial port
DB11
CS
DCLK
t
4
DOUT
DB10
DIN
PD0
t
5
t
7
t
10
t
3
t
2
BUSY
t
8
t
6
t
6
t
12
t
9
t
11
t
1
Figure 10. Detailed Timing Diagram
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| AD7843ARQ | Touch Screen Digitizer |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD7843ARQ | 制造商:Analog Devices 功能描述:TOUCH SCREEN DIGITIZER 制造商:Rochester Electronics LLC 功能描述:2.7V 12-BIT TOUCH SCREN DIGITIZER I.C. - Bulk 制造商:Analog Devices 功能描述:IC 12-BIT ADC |
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| AD7843ARQZ | 功能描述:IC ADC 12BIT TOUCHSCREEN 16-QSOP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 觸摸屏控制器 系列:- 標準包裝:96 系列:- 類型:- 觸摸面板接口:- 輸入數/鍵:- 分辨率（位）:- 評估套件:* 數據接口:- 數據速率/采樣率 (SPS，BPS):- 電壓基準:- 電源電壓:- 電流 - 電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD7843ARQZ2 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Touch Screen Digitizer |
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