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參數(shù)資料
| 型號(hào)： | AD7846AP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | LC2MOS 16-Bit Voltage Output DAC |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 7 us SETTLING TIME, 16-BIT DAC, PQCC28 |
| 封裝： | PLASTIC, MO-047AB, LCC-28 |
| 文件頁數(shù)： | 3/16頁 |
| 文件大?。?/td> | 615K |
| 代理商： | AD7846AP |
Parameter
Limit at T
MIN
to T
MAX
(All Versions)
0
60
0
60
0
120
10
60
0
70
0
70
130
Unit
Test Conditions/Comments
t
1
t
2
t
3
t
4
t
5
t
6
t
7
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns min
ns min
R/
W
to
CS
Setup Time
CS
Pulsewidth (Write Cycle)
R/
W
to
CS
Hold Time
Data Setup Time
Data Hold Time
Data Access Time
Bus Relinquish Time
t
8
t
9
t
10
t
11
t
12
CLR
Setup Time
CLR
Pulsewidth
CLR
Hold Time
LDAC
Pulsewidth
CS
Pulsewidth (Read Cycle)
NOTES
1
Timing specifications are sample tested at +25
°
C to ensure compliance. All input control signals are specified with t
R
= t
F
= 5 ns (10% to 90% of +5 V) and timed
from a voltage level of 1.6 V.
2
t
6
is measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
3
t
7
is defined as the time required for an output to change 0.5 V when loaded with the circuits of Figure 2.
Specifications subject to change without notice.
AD7846
REV. E
–3–
Limit at
T
MIN
to T
MAX
(All Versions)
Parameter
Output Settling Time
1
Unit
μ
s max
μ
s max
V/
μ
s typ
Test Conditions/Comments
To 0.006% FSR. V
OUT
loaded. V
REF–
= 0 V. Typically 3.5
μ
s.
To 0.003% FSR. V
OUT
loaded. V
REF–
= –5 V. Typically 6.5
μ
s.
6
9
7
Slew Rate
Digital-to-Analog Glitch
Impulse
70
nV-secs typ
DAC alternately loaded with 10 . . . 0000 and
01 . . . 1111. V
OUT
unloaded.
V
REF–
= 0 V, V
REF+
= 1 V rms, 10 kHz sine wave.
DAC loaded with all 0s.
DAC alternately loaded with all 1s and all 0s.
CS
High.
AC Feedthrough
0.5
mV pk-pk typ
Digital Feedthrough
Output Noise Voltage
Density 1 kHz–100 kHz
10
nV-secs typ
50
nV/
√
Hz
typ
Measured at V
OUT
. DAC loaded with 0111011 . . . 11.
V
REF+
= V
REF–
= 0 V.
NOTES
1
LDAC
= 0. Settling time does not include deglitching time of 2.5
μ
s (typ).
Specifications subject to change without notice.
TIMING CHARACTERISTICS
(V
DD
= +14.25 V to +15.75 V; V
SS
= –14.25 V to –15.75 V; V
CC
= +4.75 V to +5.25 V)
DATA
5V
t
1
t
3
t
1
t
3
t
2
t
12
t
4
t
5
t
6
t
7
DATA VALID
t
9
t
9
DATA VALID
t
9
t
8
t
10
t
8
t
10
t
11
LDAC
CLR
CS
R/
W
0V
5V
0V
5V
0V
5V
0V
5V
0V
Figure 3. Timing Diagram
Figure 2. Load Circuits for Bus Relinquish Time (t
7
)
b. V
OL
to High Z
a. V
OH
to High Z
b. High Z to V
OL
a. High Z to V
OH
Figure 1. Load Circuits for Access Time (t
6
)
AC PERFORMANCE CHARACTERISTICS
These characteristics are included for design guidance and are not
subject to test. (V
REF+
= +5 V; V
DD
= +14.25 V to +15.75 V; V
SS
= –14.25 V
to –15.75 V; V
CC
= +4.75 V to +5.25 V; R
IN
connected to 0 V.)
DBN
3k
100pF
DGND
DBN
100pF
DGND
3k
5V
DBN
3k
10pF
DGND
DBN
10pF
DGND
3k
5V
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