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參數資料
| 型號： | AD7846JN |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | LC2MOS 16-Bit Voltage Output DAC |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 7 us SETTLING TIME, 16-BIT DAC, PDIP28 |
| 封裝： | PLASTIC, MS-011, DIP-28 |
| 文件頁數： | 11/16頁 |
| 文件大?。?/td> | 615K |
| 代理商： | AD7846JN |
AD7846
REV. E
–11–
POSITION MEASUREMENT APPLICATION
Figure 22 shows the AD7846 in a position measurement appli-
cation using an LVDT (Linear Variable Displacement Trans-
ducer), an AD630 synchronous demodulator and a comparator
to make a 16-bit LVDT-to-Digital Converter. The LVDT is
excited with a fixed frequency and fixed amplitude sine wave
(usually 2.5 kHz, 2 V pk-pk). The outputs of the secondary coil
are in antiphase and their relative amplitudes depend on the
position of the core in the LVDT. The AD7846 output interpo-
lates between these two inputs in response to the DAC input
code. The AD630 is set up so that it rectifies the DAC output
signal. Thus, if the output of the DAC is in phase with the
V
REF+
input, the inverting input to the comparator will be posi-
tive, and if it is in phase with V
REF–,
the output will be negative.
By turning on each bit of the DAC in succession starting with
the MSB, and deciding to leave it on or turn it off based on the
comparator output, a 16-bit measurement of the core position is
obtained.
AD7846*
LVDT
R
IN
V
OUT
DGND
DB0
V
REF+
V
REF
–
DB15
1R1
C1
PROCESSOR DATA BUS
SIGNAL
GROUND
TO
PROCESSOR PORT
*ADDITIONAL PINS
OMITTED FOR CLARITY
–
(1
–
x)ASIN t
x ASIN t
ASIN t
AD630*
Figure 22. AD7846 in Position Measurement Application
MICROPROCESSOR INTERFACING
AD7846-to-8086 Interface
Figure 23 shows the 8086 16-bit processor interfacing to the
AD7846. The double buffering feature of the DAC is not used
in this circuit since
LDAC
is permanently tied to 0 V. AD0–
AD15 (the 16-bit data bus) are connected to the DAC data bus
(DB0–DB15). The 16-bit word is written to the DAC in one
MOV instruction and the analog output responds immediately.
In this example, the DAC address is D000H.
AD7846*
+5V
DATA BUS
*LINEAR CIRCUITRY
OMITTED FOR CLARITY
CS
LDAC
CLR
R/
W
DB0
–
DB15
16-BIT
LATCH
8086
ALE
DEN
RD
WR
AD0
–
AD15
ADDRESS
DECODE
ADDRESS BUS
Figure 23. AD7846-to-8086 Interface Circuit
In a multiple DAC system, the double buffering of the AD7846
allows the user to simultaneously update all DACs. In Figure
24, a 16-bit word is loaded to the input latches of each of the
DACs in sequence. Then, with one instruction to the appropri-
ate address,
CS4
(i.e.,
LDAC
) is brought low, updating all the
DACs simultaneously.
AD7846*
CS
LDAC
CLR
R/
W
DB0
–
DB15
+5V
DATA BUS
*LINEAR CIRCUITRY
OMITTED FOR CLARITY
16-BIT
LATCH
8086
ALE
DEN
RD
WR
AD0
–
AD15
ADDRESS
DECODE
ADDRESS BUS
AD7846*
CS
LDAC
CLR
R/
W
DB0
–
DB15
+5V
AD7846*
CS
LDAC
CLR
R/
W
DB0
–
DB15
+5V
Figure 24. AD7846-to-8086 Interface: Multiple DAC System
AD7846-to-MC68000 Interface
Interfacing between the AD7846 and MC68000 is accom-
plished using the circuit of Figure 25. The following routine
writes data to the DAC latches and then outputs the data via the
DAC latch.
1000
MOVE.W #W, D0
The desired DAC data, W,
is loaded into Data Regis-
ter 0. W may be any value
between 0 and 65535
(decimal) or 0 and FFFF
(hexadecimal).
The data, W, is transferred
between D0 and the DAC
register.
Control is returned to the
System Monitor using
these two instructions.
MOVE.W D0, $E000
MOVE.W #228, D7
TRAP
#14
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