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參數資料
| 型號： | AD7846JP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | LC2MOS 16-Bit Voltage Output DAC |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 7 us SETTLING TIME, 16-BIT DAC, PQCC28 |
| 封裝： | PLASTIC, MO-047AB, LCC-28 |
| 文件頁數： | 8/16頁 |
| 文件大小： | 615K |
| 代理商： | AD7846JP |
REV. E
–8–
AD7846
S1
V
REF+
V
REF
–
DAC1
DB15
–
DB12
DB15
–
DB12
SEGMENT 1
SEGMENT 16
S3
S15
S17
S16
S14
S4
S2
DAC2
DAC3
12 BIT DAC
DB11
–
DB0
R
R
V
OUT
R
IN
A3
A2
A1
Figure 16. D/A Conversion
Output Stage
The output stage of the AD7846 is shown in Figure 17. It is
capable of driving a 2 k
/1000 pF load. It also has a resistor
feedback network which allows the user to configure it for gains
of one or two. Table I shows the different output ranges that are
possible.
An additional feature is that the output buffer is configured as a
track-and-hold amplifier. Although normally tracking its input,
this amplifier is placed in a hold mode for approximately 2.5
μ
s
after the leading edge of
LDAC
. This short state keeps the DAC
output at its previous voltage while the AD7846 is internally
changing to its new value. So, any glitches that occur in the
transition are not seen at the output. In systems where the
LDAC
is tied permanently low, the deglitching will not be in
operation. Figures 8 and 9 show the outputs of the AD7846
without and with the deglitcher.
C1
LDAC
V
OUT
R
IN
DAC3
ONE
SHOT
10k
10k
Figure 17. Output Stage
UNIPOLAR BINARY OPERATION
Figure 18 shows the AD7846 in the unipolar binary circuit
configuration. The DAC is driven by the AD586, +5 V refer-
ence. Since R
IN
is tied to 0 V, the output amplifier has a gain of
2 and the output range is 0 V to +10 V. If a 0 V to +5 V range is
required, R
IN
should be tied to V
OUT
, configuring the output
stage for a gain of 1. Table III gives the code table for the circuit
of Figure 18.
R
IN
V
OUT
DGND
+15V
+5V
V
CC
V
DD
V
REF+
V
REF
–
R1
10k
C1
1 F
SIGNAL
GROUND
–
15V
*ADDITIONAL PINS
OMITTED FOR CLARITY
Figure 18. Unipolar Binary Operation
AD7846*
AD586
V
(0V TO +10V)
V
SS
4
Table III. Code Table for Figure 18
Binary Number
in DAC Latch
Analog Output
(V
OUT
)
MSB
1111 1111 1111 1111
1000 0000 0000 0000
0000 0000 0000 0001
0000 0000 0000 0000
LSB
+10 (65535/65536) V
+10 (32768/65536) V
+10 (1/65536) V
0
NOTE
1 LSB = 10 V/2
16
= 10 V/65536 = 152
μ
V.
Offset and gain may be adjusted in Figure 18 as follows: To
adjust offset, disconnect the V
REF–
input from 0 V, load the
DAC with all 0s and adjust the V
REF–
voltage until V
OUT
= 0 V.
For gain adjustment, the AD7846 should be loaded with all 1s
and R1 adjusted until V
OUT
= 10 (65535)/(65536) = 9.999847 V.
If a simple resistor divider is used to vary the V
REF–
voltage, it is
important that the temperature coefficients of these resistors
match that of the DAC input resistance (–300 ppm/
°
C). Other-
wise, extra offset errors will be introduced over temperature.
Many circuits will not require these offset and gain adjustments.
In these circuits, R1 can be omitted. Pin 5 of the AD586 may be
left open circuit and Pin 8 (V
REF–
) of the AD7846 tied to 0 V.
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