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參數資料
| 型號： | AD7849 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Serial Input, 14-Bit/16-Bit DAC |
| 中文描述： | 串行輸入，14-Bit/16-Bit援 |
| 文件頁數： | 3/15頁 |
| 文件大小： | 211K |
| 代理商： | AD7849 |
Limit at +25 C
(All Versions)
200
50
70
10
40
80
80
30
30
Limit at T
MIN
, T
MAX
(All Versions)
200
50
70
10
40
80
80
30
30
Parameter
t
13
t
2
t
3
t
4
t
5
t
64
t
7
t
r
t
f
Units
ns min
ns min
ns min
ns min
ns min
ns max
ns min
μ
s max
μ
s max
Conditions/Comments
SCLK Cycle Time
SYNC
to SCLK Setup Time
SYNC
to SCLK Hold Time
Data Setup Time
Data Hold Time
SCLK Falling Edge to SDO Valid
LDAC
,
CLR
Pulsewidth
Digital Input Rise Time
Digital Input Fall Time
NOTES
1
Guaranteed by characterization.
2
All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
3
SCLK mark/space ratio range is 40/60 to 60/40.
4
SDO load capacitance is 50 pF.
Specification subject to change without notice.
AD7849
REV. B
–3–
RESET SPECIFICATIONS
(These specifications apply when the device goes into the Reset mode during a power-up or
power-down sequence.) V
OUT
unloaded.
Parameter
V
A1
, Low Threshold Voltage for V
DD
, V
SS
1.2
All Versions Units
Test Conditions/Comments
This is the lower V
DD
/V
SS
threshold voltage for the reset
function. Above this, the reset is activated.
This is the higher V
DD
/V
SS
threshold voltage for the reset
function. Below this, the reset is activated. Typically 8 volts.
This is the lower threshold voltage for the reset function.
Above this, the reset is activated.
This is the higher V
CC
threshold voltage for the reset function.
Below this, the reset is activated. Typically 3 volts.
On Resistance of G2; V
DD
= 2 V; V
SS
= –2 V; I
G2
= 1 mA.
Volt max
Volts typ
Volts max
Volts min
Volt max
Volts typ
Volts max
Volts min
k
typ
0
9.5
6.4
1
0
4
2.5
1
V
B
, High Threshold Voltage for V
DD
, V
SS
V
C
, Low Threshold Voltage for V
CC
V
D
, High Threshold Voltage for V
CC
G2 R
ON
NOTES
1
A pull-down resistor (65 k
) on V
OUT
maintains 0 V output when V
DD
/V
SS
is below V
A
.
Specifications subject to change without notice.
AC PERFORMANCE CHARACTERISTICS
(These characteristics are included for Design Guidance and are not
subject to test. (V
REF+
= +5 V; V
DD
= +14.25 V to +15.75 V; V
SS
= –14.25 V to –15.75 V; V
CC
= +4.75 V to +5.25 V; R
OFS
connected to 0 V.)
TIMING CHARACTERISTICS
1, 2
(V
DD
= +14.25 V to +15.75 V; V
SS
= –14.25 V to –15.75 V; V
CC
= +4.75 V to +5.25 V;
R
L
= 2 k
, C
L
= 200 pF. All Specifications T
MIN
to T
MAX
unless otherwise noted.)
T
Version
A, B, C
Versions
Parameter
DYNAMIC PERFORMANCE
Output Settling Time
1
Units
Test Conditions/Comments
7
10
4
250
7
10
4
250
μ
s typ
μ
s typ
V/
μ
s typ
nV-s typ
To 0.006% FSR. V
OUT
Loaded. V
REF–
= 0 V.
To 0.003% FSR. V
OUT
Loaded. V
REF–
= –5 V.
Slew Rate
Digital-to-Analog Glitch Impulse
DAC Alternately Loaded with 00 . . . 00 and
111 . . . 11. V
OUT
Unloaded.
LDAC
Perma-
nently Low.
BIN
/COMP Set to 1. V
REF–
= –5 V.
LDAC
Frequency = 100 kHz
V
REF–
= 0 V, V
REF+
= 1 V rms, 10 kHz Sine Wave.
DAC Loaded with All 0s.
BIN
/COMP Set to 0.
DAC Alternately Loaded with All 1s and All 0s.
SYNC
High.
150
1
150
1
nV-s typ
mV pk-pk typ
AC Feedthrough
Digital Feedthrough
5
5
nV-s typ
Output Noise Voltage Density
1 kHz–100 kHz
80
80
nV/
√
Hz
typ
Measured at V
OUT
. V
REF+
= V
REF–
= 0 V.
BIN
/COMP Set to 0.
NOTES
1
LDAC
= 0. Settling time does not include deglitching time of 5
μ
s (typ).
Specification subject to change without notice.
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