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參數(shù)資料
| 型號： | AD7853 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 3 V to 5 V Single Supply, 200 KSPS 12-Bit Sampling ADCs(單電源,200kSPS 12位采樣A/D轉(zhuǎn)換器) |
| 中文描述： | 3 V至5 V單電源，200 ksps的12位采樣ADC（單電源，速度高達(dá)200ksps的12位采樣的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 22/34頁 |
| 文件大小： | 350K |
| 代理商： | AD7853 |
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REV. B
–22–
AD7853/AD7853L
System Gain and Offset Interaction
The inherent architecture of the AD7853/AD7853L leads to an
interaction between the system offset and gain errors when a
system calibration is performed. Therefore it is recommended to
perform the cycle of a system offset calibration followed by a
system gain calibration twice. Separate system offset and system
gain calibrations reduce the offset and gain errors to at least the
12-bit level. By performing a system offset calibration first and a
system gain calibration second, priority is given to reducing the
gain error to zero before reducing the offset error to zero. If the
system errors are small, a system offset calibration would be
performed, followed by a system gain calibration. If the systems
errors are large (close to the specified limits of the calibration
range), this cycle would be repeated twice to ensure that the
offset and gain errors were reduced to at least the 12-bit level.
The advantage of doing separate system offset and system gain
calibrations is that the user has more control over when the
analog inputs need to be at the required levels, and the
CONVST
signal does not have to be used.
Alternatively, a system (gain + offset) calibration can be per-
formed. It is recommended to perform three system (gain +
offset) calibrations to reduce the offset and gain errors to the
12-bit level. For the system (gain + offset) calibration priority is
given to reducing the offset error to zero before reducing the
gain error to zero. Thus if the system errors are small then two
system (gain + offset) calibrations will be sufficient. If the sys-
tem errors are large (close to the specified limits of the calibra-
tion range), three system (gain + offset) calibrations may be
required to reduced the offset and gain errors to at least the
12-bit level. There will never be any need to perform more than
three system (offset + gain) calibrations.
In Bipolar Mode the midscale error is adjusted for an offset
calibration and the positive full-scale error is adjusted for the
gain calibration; in Unipolar Mode the zero-scale error is ad-
justed for an offset calibration and the positive full-scale error is
adjusted for a gain calibration.
System Calibration Timing
The calibration timing diagram in Figure 31 is for a full system
calibration where the falling edge of
CAL
initiates an internal
reset before starting a calibration (
note that if the part is in power-
down mode the
CAL
pulsewidth must take account of the power-up
time)
. If a full system calibration is to be performed in software,
it is easier to perform separate gain and offset calibrations so
that the CONVST bit in the control register does not have to be
programmed in the middle of the system calibration sequence.
The rising edge of
CAL
starts calibration of the internal DAC
and causes the BUSY line to go high. If the control register is
set for a full system calibration, the
CONVST
must be used
also. The full-scale system voltage should be applied to the
analog input pins from the start of calibration. The BUSY line
will go low once the DAC and system gain calibration are
complete. Next the system offset voltage is applied to the AIN
pin for a minimum setup time (t
SETUP
) of 100 ns before the
rising edge of the
CONVST
and remain until the BUSY signal
goes low. The rising edge of the
CONVST
starts the system
offset calibration section of the full system calibration and also
causes the BUSY signal to go high. The BUSY signal will go
low after a time t
CAL2
when the calibration sequence is complete.
The timing for a system (gain + offset) calibration is very similar
to that of Figure 31, the only difference being that the time
t
CAL1
will be replaced by a shorter time of the order of t
CAL2
as
the internal DAC will not be calibrated. The BUSY signal will
signify when the gain calibration is finished and when the part is
ready for the offset calibration.
t
1
= 100ns MIN,
t
14
= 50/90ns MIN 5V/3V,
t
15
= 2.5
t
CLKIN
MAX,
t
CAL1
= 111114
t
CLKIN
MAX,
t
CAL2
= 13899
t
CLKIN
(I/P)
BUSY (O/P)
(I/P)
t
1
AIN (I/P)
t
15
t
CAL1
t
CAL2
t
16
t
SETUP
V
SYSTEM FULL SCALE
V
OFFSET
Figure 31. Timing Diagram for Full System Calibration
The timing diagram for a system offset or system gain calibra-
tion is shown in Figure 32. Here again the
CAL
is pulsed and
the rising edge of the
CAL
initiates the calibration sequence (or
the calibration can be initiated in software by writing to the
control register). The rising edge of the
CAL
causes the BUSY
line to go high and it will stay high until the calibration sequence is
finished. The analog input should be set at the correct level for a
minimum setup time (t
SETUP
) of 100 ns before the rising edge of
CAL
and stay at the correct level until the BUSY signal goes
low.
(I/P)
BUSY (O/P)
AIN (I/P)
t
15
t
SETUP
t
1
t
CAL2
V
SYSTEM FULL SCALE
OR V
SYSTEM OFFSET
Figure 32. Timing Diagram for System Gain or System
Offset Calibration
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD7853AN | 3 V to 5 V Single Supply, 200 kSPS 12-Bit Sampling ADCs |
| AD7853AR | 3 V to 5 V Single Supply, 200 kSPS 12-Bit Sampling ADCs |
| AD7853ARS | 3 V to 5 V Single Supply, 200 kSPS 12-Bit Sampling ADCs |
| AD7853BN | 3 V to 5 V Single Supply, 200 kSPS 12-Bit Sampling ADCs |
| AD7853BR | 3 V to 5 V Single Supply, 200 kSPS 12-Bit Sampling ADCs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7853AN | 制造商:Analog Devices 功能描述:ADC Single SAR 200ksps 12-bit Serial 24-Pin PDIP 制造商:Analog Devices 功能描述:ADC SGL SAR 200KSPS 12-BIT SERL 24PDIP - Rail/Tube 制造商:Rochester Electronics LLC 功能描述:SELF CAL.SERIAL 12-BIT ADC I.C. - Bulk 制造商:Analog Devices 功能描述:3 V to 5 V Single Supply, 200 kSPS 12-Bit Sampling ADCs |
| AD7853ANZ | 功能描述:IC ADC 12BIT SRL 200KSPS 24-DIP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
| AD7853AR | 制造商:Analog Devices 功能描述:ADC Single SAR 200ksps 12-bit Serial 24-Pin SOIC W 制造商:Rochester Electronics LLC 功能描述:SELF CAL.SERIAL 12-BIT ADC I.C. - Bulk |
| AD7853AR-REEL | 制造商:Analog Devices 功能描述:ADC Single SAR 200ksps 12-bit Serial 24-Pin SOIC W T/R |
| AD7853ARS | 制造商:Analog Devices 功能描述:ADC Single SAR 200ksps 12-bit Serial 24-Pin SSOP 制造商:Rochester Electronics LLC 功能描述:SELF CAL.SERIAL 12-BIT ADC I.C. - Bulk |
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