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參數資料
| 型號： | AD7853ARS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 3 V to 5 V Single Supply, 200 kSPS 12-Bit Sampling ADCs |
| 中文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO24 |
| 封裝： | SSOP-24 |
| 文件頁數： | 30/34頁 |
| 文件大?。?/td> | 350K |
| 代理商： | AD7853ARS |
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REV. B
–30–
AD7853/AD7853L
MICROPROCESSOR INTERFACING
In many applications, the user may not require the facility of
writing to the on-chip registers. The user may just want to
hardwire the relevant pins to the appropriate levels and read the
conversion result. In this case the DIN pin can be tied low so
that the on-chip registers are never used. Now the part will
operate as a nonprogrammable analog to digital converter where
the
CONVST
is applied, a conversion is performed and the
result may be read using the SCLK to clock out the data from
the output register on to the DOUT pin. Note that the DIN pin
cannot be tied low when using the two-wire interface mode of
operation.
The SCLK can also be connected to the CLKIN pin if the user
does not want to have to provide separate serial and master
clocks in Interface Modes 1, 2, and 3. With this arrangement
the
SYNC
signal must be low for 16 SCLK cycles in Interface
Modes 1 and 2 for the read and write operations. For Interface
Mode 3 the
SYNC
can be low for more than 16 SCLK cycles
for the read and write operations. Note that in Interface Modes
4 and 5 the CLKIN and SCLK cannot be tied together as the
SCLK is an output and the CLKIN is an input.
DIN
DOUT
SYNC
CONVST
CLKIN
SCLK
AD7853/AD7853L
4 MHz/1.8MHz
MASTER
CLOCK
SYNC
SIGNAL
TO GATE
THE SCLK
SERIAL DATA
OUTPUT
CONVERSION
START
Figure 44. Simplified Interface Diagram with DIN
Grounded and SCLK Tied to CLKIN
AD7853/AD7853L to 8XC51/PIC17C42 Interface
Figure 45 shows the AD7853/AD7853L interface to the 8XC51/
PIC17C42. The 8XL51 is for interfacing to the AD7853/AD7853L
when the supply is at 3 V. The 8XC51/PIC17C42 only run at
5 V. The 8XC51 is in Mode 0 operation. This is a two-wire
interface consisting of the SCLK and the DIN which acts as a
bidirectional line. The
SYNC
is tied low. The BUSY line can be
used to give an interrupt driven system but this would not nor-
mally be the case with the 8XC51/PIC17C42. For the 8XC51
12 MHz version, the serial clock will run at a maximum of
1 MHz so that the serial interface to the AD7853/AD7853L will
only be running at 1 MHz. The CLKIN signal must be provided
separately to the AD7853/AD7853L from a port line on the
8XC51 or from a source other than the 8XC51. Here the SCLK
cannot be tied to the CLKIN as the 8XC51 only provides a
noncontinuous serial clock. The
CONVST
signal can be pro-
vided from an external timer or conversion can be started in
software if required. The sequence of events would typically be
writing to the control register via the DIN line setting a conver-
sion start and the 2-wire interface mode (this would be per-
formed in two 8-bit writes), wait for the conversion to be
finished (4.5
μ
s with 4 MHz CLKIN), read the conversion re-
sult data on the DIN line (this would be performed in two 8-bit
reads), and then repeat the sequence. The maximum serial
frequency will be determined by the data access and hold times
of the 8XC51/PIC16C42 and the AD7853/AD7853L.
(8XC51/L51)
/PIC17C42
P3.0/DT
P3.1/CK
AD7853/AD7853L
CONVST
CLKIN
SCLK
DIN
SYNC
SM1
SM2
POLARITY
OPTIONAL
4MHz/1.8MHz
BUSY
(
INT0
/P3.2)/INT
DV
FOR 8XC51/L51
DGND FOR PIC17C42
MASTER
SLAVE
OPTIONAL
Figure 45. 8XC51/PIC17C42 Interface
AD7853/AD7853L to 68HC11/16/L11/PIC16C42 Interface
Figure 46 shows the AD7853/AD7853L SPI/QSPI interface to
the 68HC11/16/L11/PIC16C42. The 68L11 is for interfacing to
the AD7853/AD7853L when the supply is at 3 V. The
SYNC
line is not used and is tied to DGND. The
μ
Controller is config-
ured as the master, by setting the MSTR bit in the SPCR to 1,
and thus provides the serial clock on the SCK pin. For all the
μ
Controllers, the CPOL bit is set to 1 and for the 68HC11/16/
L11, the CPHA bit is set to 1. The CLKIN and
CONVST
signals can be supplied from the
μ
Controller or from separate
sources. The BUSY signal can be used as an interrupt to tell the
μ
Controller when the conversion is finished, then the reading
and writing can take place. If required the reading and writing
can take place during conversion and there will be no need for
the BUSY signal in this case. For no writing to the part then the
DIN pin can be tied permanently low. For the 68HC16 and the
QSPI interface the SM2 pin should be tied high and the
SS
line
tied to the
SYNC
pin. The microsequencer on the 68HC16
QSPI port can be used for performing a number of read and
write operations independent of the CPU and storing the con-
version results in memory without taxing the CPU. The typical
sequence of events would be writing to the control register via
the DIN line setting a conversion start and at the same time
reading data from the previous conversion on the DOUT line,
wait for the conversion to be finished (4.5
μ
s with 4 MHz
CLKIN), and then repeat the sequence. The maximum serial
frequency will be determined by the data access and hold times
of the
μ
Controllers and the AD7853/AD7853L.
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