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參數資料
| 型號： | AD7853LAN |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 3 V to 5 V Single Supply, 200 kSPS 12-Bit Sampling ADCs |
| 中文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDIP24 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-24 |
| 文件頁數： | 3/34頁 |
| 文件大小： | 350K |
| 代理商： | AD7853LAN |
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Parameter
A Version
1
B Version
1
Units
Test Conditions/Comments
LOGIC OUTPUTS
Output High Voltage, V
OH
I
SOURCE
= 200
μ
A
AV
DD
= DV
DD
= 4.5 V to 5.5 V
AV
DD
= DV
DD
= 3.0 V to 3.6 V
I
SINK
= 0.8 mA
4
2.4
0.4
±
10
4
2.4
0.4
±
10
10
V min
V min
V max
μ
A max
pF max
Output Low Voltage, V
OL
Floating-State Leakage Current
Floating-State Output Capacitance
4
10
Output Coding
Straight (Natural) Binary
Twos Complement
Unipolar Input Range
Bipolar Input Range
CONVERSION RATE
Conversion Time
4.6 (18)
4.6 (18)
(10)
0.4 (1)
μ
s max
μ
s max
μ
s min
(L Versions Only, –40
°
C to +85
°
C, 1 MHz CLKIN)
(L Versions Only, 0
°
C to +70
°
C, 1.8 MHz CLKIN)
(L Versions Only)
Track/Hold Acquisition Time
0.4 (1)
POWER REQUIREMENTS
AV
DD,
DV
DD
I
DD
Normal Mode
5
+3.0/+5.5
+3.0/+5.5
V min/max
6 (1.9)
5.5 (1.9)
6 (1.9)
5.5 (1.9)
mA max
mA max
AV
DD
= DV
DD
= 4.5 V to 5.5 V. Typically 4.5 mA (1.5);
AV
DD
= DV
DD
= 3.0 V to 3.6 V. Typically 4.0 mA (1.5 mA)
Sleep Mode
6
With External Clock On
10
10
μ
A typ
Full Power-Down. Power Management Bits in Control Register
Set as PMGT1 = 1, PMGT0 = 0
Partial Power-Down. Power Management Bits in Control
Register Set as PMGT1 = 1, PMGT0 = 1
Typically 1
μ
A. Full-Power Down. Power Management Bits in
Control Register Set as PMGT1 = 1, PMGT0 = 0
Partial Power-Down. Power Management Bits in Control
Register Set as PMGT1 = 1, PMGT0 = 1
V
DD
= 5.5 V: Typically 25 mW (8);
SLEEP
= V
DD
V
DD
= 3.6 V: Typically 15 mW (5.4);
SLEEP
= V
DD
400
400
μ
A typ
With External Clock Off
5
5
μ
A max
200
200
μ
A typ
Normal Mode Power Dissipation
33 (10.5)
20 (6.85)
33 (10.5)
20 (6.85)
mW max
mW max
Sleep Mode Power Dissipation
With External Clock On
55
36
27.5
18
55
36
27.5
18
μ
W typ
μ
W typ
μ
W max
μ
W max
V
DD
= 5.5 V;
SLEEP
= 0 V
V
DD
= 3.6 V;
SLEEP
= 0 V
V
DD
= 5.5 V: Typically 5.5
μ
W;
SLEEP
= 0 V
V
DD
= 3.6 V: Typically 3.6
μ
W;
SLEEP
= 0 V
With External Clock Off
SYSTEM CALIBRATION
Offset Calibration Span
7
Gain Calibration Span
7
+0.05
×
V
REF
/–0.05
×
V
REF
+1.025
×
V
REF
/–0.975
×
V
REF
V max/min
V max/min
Allowable Offset Voltage Span for Calibration
Allowable Full-Scale Voltage Span for Calibration
NOTES
1
Temperature ranges as follows: A, B Versions, –40
°
C to +85
°
C. For L Versions, A and B Versions f
CLKIN
= 1 MHz over –40
°
C to +85
°
C temperature range,
B Version f
= 1.8 MHz over 0
°
C to +70
°
C temperature range.
2
Specifications apply after calibration.
3
SNR calculation includes distortion and noise components.
4
Sample tested @ +25
°
C to ensure compliance.
5
All digital inputs @ DGND except for
CONVST
,
SLEEP
,
CAL
, and
SYNC
@ DV
. No load on the digital outputs. Analog inputs @ AGND.
6
CLKIN @ DGND when external clock off. All digital inputs @ DGND except for
CONVST
,
SLEEP
,
CAL
, and
SYNC
@ DV
DD
. No load on the digital outputs.
Analog inputs @ AGND.
7
The offset and gain calibration spans are defined as the range of offset and gain errors that the AD7853/AD7853L can calibrate. Note also that these are voltage spans
and are not absolute voltages (i.e., the allowable system offset voltage presented at AIN(+) for the system offset error to be adjusted out will be AIN(–)
±
0.05
×
V
REF
,
and the allowable system full-scale voltage applied between AIN(+) and AIN(–) for the system full-scale voltage error to be adjusted out will be V
REF
±
0.025
×
V
REF
).
This is explained in more detail in the calibration section of the data sheet.
Specifications subject to change without notice.
AD7853/AD7853L
REV. B
–3–
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