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參數(shù)資料
| 型號(hào)： | AD7862BR-3 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Simultaneous Sampling Dual 250 kSPS 12-Bit ADC |
| 中文描述： | 2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁(yè)數(shù)： | 9/16頁(yè) |
| 文件大小： | 414K |
| 代理商： | AD7862BR-3 |
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AD7862
–9–
REV. 0
and fourth read pulses, after the second conversion and A0 high,
access the result from Channel B (V
B1
and V
B2
respectively). A0’s
state can be changed any time after the
CONVST
goes high,
i.e., track/holds into hold, and 400 ns prior to the next falling
edge of
CONVST
. Data is read from the part via a 12-bit
parallel data bus with standard
CS
and
RD
signal, i.e., the read
operation consists of a negative going pulse on the
CS
pin
combined with two negative going pulses on the
RD
pin (while
the
CS
is low), accessing the two 12-bit results. Once the read
operation has taken place, a further 300 ns should be allowed
before the next falling edge of
CONVST
to optimize the settling
of the track/hold amplifier before the next conversion is initiated.
With the internal clock frequency at its maximum (3.7 MHz—not
accessible externally), the achievable throughput rate for the
part is 3.6
μ
s (conversion time) plus 100 ns (read time) plus
0.3
μ
s (acquisition time). This results in a minimum throughput
time of 4
μ
s (equivalent to a throughput rate of 250 kHz).
Read Options
Apart from the read operation described above and displayed in
Figure 5a, other
CS
and
RD
combinations can result in
different channels/inputs being read in different combinations.
Suitable combinations are shown in Figures 5b through 5d.
V
A1
V
A2
CS
RD
DATA
Figure 5b. Read Option A
V
A1
V
A2
CS
RD
DATA
V
A1
Figure 5c. Read Option B
V
A1
V
B1
A0
CS
RD
DATA
Figure 5d. Read Option C
OPERATING MODES
Mode 1 Operation (High Sampling Performance)
The timing diagram in Figure 5a is for optimum performance in
operating mode 1 where the falling edge of
CONVST
starts
conversion and puts the track/hold amplifiers into their hold
mode. This falling edge of
CONVST
also causes the BUSY
signal to go high to indicate that a conversion is taking place.
The BUSY signal goes low when the conversion is complete,
which is 3.6
μ
s max after the falling edge of
CONVST
, and new
data from this conversion is available in the output latch of the
AD7862. A read operation accesses this data. If the multiplexer
select A0 is low, the first and second read pulses after the first
conversion access the result from Channel A (V
A1
and V
A2
V
A1
V
A2
V
B1
V
B2
t
3
t
1
t
2
t
4
t
5
t
6
t
CONV
= 3.6μs
t
7
CONVST
BUSY
A0
CS
RD
DATA
300ns
400ns
Figure 5a. Mode 1 Timing Operation Diagram for High Sampling Performance
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| AD7862BRZ-10 | 功能描述:IC ADC 12BIT DUAL 250KSPS 28SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個(gè)單端，雙極 |
| AD7862BRZ-10REEL | 功能描述:IC ADC 12BIT DUAL 250KSPS 28SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個(gè)單端，單極；1 個(gè)單端，雙極 |
| AD7862BRZ-3 | 功能描述:IC ADC 12BIT DUAL 250KSPS 28SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個(gè)單端，雙極 |
| AD7862SQ-10 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Simultaneous Sampling Dual 250 kSPS 12-Bit ADC |
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