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參數(shù)資料
| 型號： | AD7864AS-3 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 4-Channel, Simultaneous Sampling, High Speed, 12-Bit ADC |
| 中文描述： | 4-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PQFP44 |
| 封裝： | PLASTIC, MO-112-AA, MQFP-44 |
| 文件頁數(shù)： | 6/19頁 |
| 文件大小： | 214K |
| 代理商： | AD7864AS-3 |
AD7864
–6–
REV. A
PIN FUNCTION DESCRIPTION
Pin
Mnemonic
Description
1
BUSY
Busy Output. The busy output is triggered high by the rising edge of
CONVST
and remains high until
conversion is completed on all selected channels.
First Data Output. FRSTDATA is a logic output which, when high, indicates that the Output Data
Register Pointer is addressing Register 1—See Accessing the Output Data Registers.
Convert Start Input. Logic Input. A low-to-high transition on this input puts all track/holds into their
hold mode and starts conversion on the selected channels. In addition, the state of the Channel Sequence
Selection is also latched on the rising edge of
CONVST
.
Chip Select Input. Active Low Logic Input. The device is selected when this input is active.
Read Input. Active Low Logic Input that is used in conjunction with
CS
low to enable the data out-
puts. Ensure the
WR
pin is at logic high while performing a read operation.
Write Input. A rising edge on the
WR
input, with
CS
low and
RD
high, latches the logic state on DB0
to DB3 into the channel select register.
Hardware Channel Select. Conversion sequence selection can also be made via the SL1–SL4 pins if
H
/S SEL is logic zero. The selection is latched on the rising edge of
CONVST
. See Selecting a Conver-
sion Sequence.
Hardware/Software Select Input. When this pin is at a Logic 0, the AD7864 conversion sequence selec-
tion is controlled via the SL1–SL4 input pins. When this pin is at Logic 1, the sequence is controlled
via the channel select register. See Selecting a Conversion Sequence.
Analog Ground. General Analog Ground. This AGNDpin should be connected to the system’s
AGND
plane.
Analog Inputs. See Analog Input section.
Analog Ground. Analog Ground reference for the attenuator circuitry. This AGNDpin should be
connected to the system’s AGND
plane.
Analog Inputs. See Analog Input section.
Standby Mode Input. TTL-compatible input that is used to put the device into the power save or
standby mode. The
STBY
input is high for normal operation and low for standby operation.
Reference Ground. Ground reference for the part’s on-chip reference buffer. The V
REF
GND pin
should be connected to the system’s AGND
plane.
Reference Input/Output. This pin provides access to the internal reference (2.5 V
±
5%) and also
allows the internal reference to be overdriven by an external reference source (2.5 V). A 0.1
μ
F decou-
pling capacitor should be connected between this pin and AGND.
Analog Positive Supply Voltage, +5.0 V
±
5%.
Analog Ground. Analog Ground reference for the DAC circuitry.
Internal/External Clock Select Input. When this pin is at a Logic 0, the AD7864 uses its internally
generated master clock. When this pin is at Logic 1, the master clock is generated externally to the
device.
Conversion Clock Input. This is an externally applied clock that allows the user to control the conver-
sion rate of the AD7864. Each conversion needs fourteen clock cycles in order for the conversion to be
completed and an
EOC
pulse to be generated. The clock should have a duty cycle that is no worse than
60/40. See Using an External Clock.
Data Bit 11 is the MSB, followed by Data Bit 10 to Data Bit 6. Three-state TTL outputs. Output
coding is 2s complement for the AD7864-1 and AD7864-3. Output coding is straight (natural) binary
for the AD7864-2.
Positive supply voltage for digital section, +5.0 V
±
5%. A 0.1
μ
F decoupling capacitor should be con-
nected between this pin and AGND. Both DV
DD
and AV
DD
should be externally tied together.
This pin provides the positive supply voltage for the output drivers (DB0 to DB11), BUSY,
EOC
and
FRSTDATA. It is normally tied to DV
DD
. V
DRIVE
should be decoupled with a 0.1
μ
F capacitor. It allows
improved performance when reading during the conversion sequence. To facilitate interfacing to 3 V proces-
sors and DSPs the output data drivers may also be powered by a 3 V
±
10% supply .
Digital Ground. Ground reference for digital circuitry. This DGND pin should be connected to the
system’s AGND
plane at the AGND pin.
Data Bit 5 to Data Bit 4. Three-state TTL Outputs.
Data Bit 3 to Data Bit 0. Bidirectional Data Pins. When a read operation takes place, these pins are three-
state TTL outputs. The channel select register is programmed with the data on the DB0–DB3 pins with
standard
CS
and
WR
signals. DB0 represents Channel 1 and DB3 which represents Channel 4.
End-of-Conversion. Active low logic output indicating conversion status. The end of each conversion in
a conversion sequence is indicated by a low-going pulse on this line.
2
FRSTDATA
3
CONVST
4
5
CS
RD
6
WR
7–10
SL1–SL4
11
H
/S SEL
12
AGND
13–16
17
V
IN4X
, V
IN3X
AGND
18–21
22
V
IN2X
, V
IN1X
STBY
23
V
REF
GND
24
V
REF
25
26
27
AV
DD
AGND
INT
/EXT CLK
28
CLKIN
29–34
DB11–DB6
35
DV
DD
36
V
DRIVE
37
DGND
38, 39
40–43
DB5, DB4
DB3–DB0
44
EOC
相關PDF資料 |
PDF描述 |
|---|---|
| AD7864AS | IC-SM-12-BIT ADC |
| AD7865YS-1 | Four-Channel, Simultaneous Sampling, Fast, 14-Bit ADC |
| AD7865YS-2 | Four-Channel, Simultaneous Sampling, Fast, 14-Bit ADC |
| AD7865YS-3 | Four-Channel, Simultaneous Sampling, Fast, 14-Bit ADC |
| AD7865AS-1 | Four-Channel, Simultaneous Sampling, Fast, 14-Bit ADC |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD7864AS-3REEL | 制造商:Analog Devices 功能描述:ADC Single SAR 520ksps 12-bit Parallel 44-Pin MQFP T/R |
| AD7864AS-3Z | 制造商:Analog Devices 功能描述:ADC 12BIT 4CH 500KSPS 44MQ 制造商:Analog Devices 功能描述:ADC, 12BIT, 4CH, 500KSPS, 44MQFP; Resolution (Bits):12bit; Sampling Rate:520kSPS; Supply Voltage Type:Single; Supply Voltage Min:4.75V; Supply Voltage Max:5.25V; Supply Current:24mA; Digital IC Case Style:MQFP; No. of Pins:44; Input ;RoHS Compliant: Yes |
| AD7864ASZ-1 | 功能描述:IC ADC 12BIT DUAL 4CH 44-MQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉換器 系列:- 標準包裝:1 系列:microPOWER™ 位數(shù):8 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，SPI? 轉換器數(shù)目:1 功率耗散（最大）:- 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應商設備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數(shù)目和類型:8 個單端，單極 產(chǎn)品目錄頁面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6 |
| AD7864ASZ-12 | 制造商:AD 制造商全稱:Analog Devices 功能描述:4-Channel, Simultaneous Sampling, High Speed, 12-Bit ADC |
| AD7864ASZ-1KL1 | 制造商:Analog Devices 功能描述: |
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