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參數資料
| 型號： | AD7865AS-3 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Four-Channel, Simultaneous Sampling, Fast, 14-Bit ADC |
| 中文描述： | 4-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁數： | 4/19頁 |
| 文件大小： | 195K |
| 代理商： | AD7865AS-3 |
AD7865
TIMING CHARACTERISTICS
1, 2
–4–
REV. A
Parameter
A, B, Y Versions
Units
μ
s max
μ
s max
μ
s max
Test Conditions/Comments
t
CONV
2.4
3.2
0.35
No. of Channels
×
(t
CONV
)
1
35
70
Conversion Time, Internal Clock
Conversion Time, External Clock (5 MHz)
Acquisition Time
Selected Number of Channels Multiplied by t
CONV
t
ACQ
t
BUSY
μ
s max
μ
s max
ns min
ns min
t
WAKE-UP
—External V
REF3
t
1
t
2
Read Operation
t
3
t
4
t
5
t
64
STBY
Rising Edge to
CONVST
Rising Edge
CONVST
Pulsewidth
CONVST
Rising Edge to BUSY Rising Edge
0
0
35
35
40
5
30
15
120
180
70
15
0
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns min
ns min
ns max
ns max
ns max
ns min
CS
to
RD
Setup Time
CS
to
RD
Hold Time
Read Pulsewidth
Data Access Time After Falling Edge of
RD
, V
DRIVE
= 5 V
Data Access Time After Falling Edge of
RD
, V
DRIVE
= 3 V
Bus Relinquish Time After Rising Edge of
RD
t
75
t
8
t
9
Time Between Consecutive Reads
EOC
Pulsewidth
t
10
t
11
t
12
RD
Rising Edge to FRSTDATA Edge (Rising or Falling)
EOC
Falling Edge to FRSTDATA Falling Delay
EOC
to
RD
Delay
Write Operation
t
13
t
14
t
15
t
16
t
17
External Clock
t
18
20
0
0
5
5
ns min
ns min
ns min
ns min
ns min
WR
Pulsewidth
CS
to
WR
Setup Time
WR
to
CS
Hold Time
Input Data Setup Time of Rising Edge of
WR
Input Data Hold Time
200
ns min
CONVST
Falling Edge to CLK Rising Edge
NOTES
1
Sample tested at +25
°
C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of +5 V) and timed from a voltage level of +1.6V.
2
See Figures 6, 7 and 8.
3
Refer to the Standby Mode Operation section. The MAX specification of 1
μ
s is valid when using a 0.1
μ
F decoupling capacitor on the V
REF
pin.
4
Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8V or 2.4 V.
5
These times are derived from the measured time taken by the data outputs to change 0.5V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
Specifications subject to change without notice.
1.6mA
50pF
TO OUTPUT
PIN
+1.6V
400
m
A
Figure 1. Load Circuit for Access Time and Bus Relinquish Time
(V
DD
= +5 V
6
5%, AGND = DGND = 0 V, V
REF
= Internal, Clock = Internal; all specifications
T
MIN
to T
MAX
unless otherwise noted.)
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| AD7865AS-3REEL | 制造商:Analog Devices 功能描述:ADC Single SAR 350ksps 14-bit Parallel 44-Pin MQFP T/R |
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| AD7865ASZ-1REEL | 功能描述:IC ADC 14BIT 4CHAN 5V 44-MQFP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 標準包裝:1,000 系列:- 位數:12 采樣率（每秒）:300k 數據接口:并聯 轉換器數目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數目和類型:1 個單端，單極；1 個單端，雙極 |
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