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參數(shù)資料
| 型號： | AD7868AN |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | LC2MOS Complete, 12-Bit Analog I/O System |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDIP24 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-24 |
| 文件頁數(shù)： | 5/16頁 |
| 文件大小： | 337K |
| 代理商： | AD7868AN |
AD7868
–5–
REV. B
PIN FUNCT ION DE SCRIPT ION
DIP Pin
Number
Mnemonic
Function
POWER SUPPLY
7 & 23
10 & 22
8 & 19
6 &17
V
DD
V
SS
AGND
DGND
Positive Power Supply, 5 V
±
5%. Both V
DD
pins must be tied together.
Negative Power Supply, –5 V
±
5%. Both V
SS
pins must be tied together.
Analog Ground. Both AGND pins must be tied together.
Digital Ground. Both DGND pins must be tied together.
ANALOG SIGNAL AND REFERENCE
21
V
IN
9
V
OUT
ADC Analog Input. T he ADC input range is
±
3 V.
Analog Output Voltage from DAC. T his output comes from a buffer amplifier. T he range is
bipolar,
±
3 V with RI DAC = +3 V.
Voltage Reference Output. T he internal ADC 3 V reference is provided at this pin. T his output may be
used as a reference for the DAC by connecting it to the RI DAC input. T he external load capability of
this reference is 500
μ
A.
DAC Voltage Reference Output. T his is one of two internal voltage references. T o operate the DAC
with this internal reference, RO DAC should be connected to RI DAC. T he external load capability of
the reference is 500
μ
A.
DAC Voltage Reference Input. T he voltage reference for the DAC must be applied to this pin. It is
internally buffered before being applied to the DAC. T he nominal reference voltage for correct
operation of the AD7868 is 3 V.
20
RO ADC
11
RO DAC
12
RI DAC
ADC INT ERFACE AND CONT ROL
2
CLK
Clock Input. An external T T L-compatible clock may be applied to this input. Alternatively, tying pin to
V
SS
enables the internal laser-trimmed oscillator.
Receive Frame Synchronization, Logic Output. T his is an active low open-drain output which provides
a framing pulse for serial data. An external 4.7 k
pull-up resistor is required on
RFS
.
Receive Clock, Logic Output. RCLK is the gated serial clock output which is derived from the internal
or external ADC clock. If the CONT ROL input is at V
SS
the clock runs continuously. With the
CONT ROL input at DGND the RCLK output is gated off (three-stated) after serial transmission is
complete. RCLK is an open-drain output and requires an external 2 k
pull-up resistor.
Receive Data, Logic Output. T his is an open-drain data output used in conjunction with
RFS
and
RCLK to transmit data from the ADC. Serial data is valid on the falling edge of RCLK when
RFS
is
low. An external 4.7 k
resistor is required on the DR output.
Convert Start, Logic Input. A low to high transition on this input puts the track-and-hold amplifier into
the hold mode and starts an ADC conversion. T his input in asynchronous to the CLK input.
Control, Logic Input. With this pin at 0 V, the RCLK is noncontinuous. With this pin at –5 V, the
RCLK is continuous. Note, tying this pin to V
DD
places the part in a factory test mode where normal
operation is not exhibited.
3
RFS
4
RCLK
5
DR
1
CONVST
24
CONT ROL
DAC INT ERFACE AND CONT ROL
14
TFS
T ransmit Frame Synchronization, Logic Input. T his is a frame or synchronization signal for the DAC
with serial data expected after the falling edge of this signal.
T ransmit Data, Logic Input. T his is the data input which is used in conjunction with
TFS
and T CLK
to transfer serial data to the input latch.
T ransmit Clock, Logic Input. Serial data bits are latched on the falling edge of T CLK when
TFS
is low.
Load DAC, Logic Input. A new word is transferred into the DAC latch from the input latch on the
falling edge of this signal.
No Connect.
15
DT
16
13
T CLK
LDAC
18
NC
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD7868AQ | LC2MOS Complete, 12-Bit Analog I/O System |
| AD7868AR | LC2MOS Complete, 12-Bit Analog I/O System |
| AD7868BN | LC2MOS Complete, 12-Bit Analog I/O System |
| AD7868BQ | LC2MOS Complete, 12-Bit Analog I/O System |
| AD7868BR | LC2MOS Complete, 12-Bit Analog I/O System |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7868ANZ | 功能描述:IC I/O PORT 12BIT ANLG 24-DIP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
| AD7868AQ | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD7868AR | 功能描述:IC I/O PORT 12BIT ANLG 28-SOIC RoHS:否 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
| AD7868AR-REEL | 功能描述:IC I/O PORT 12BIT ANLG 28-SOIC RoHS:否 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
| AD7868ARZ | 功能描述:IC I/O PORT 12BIT ANLG 28-SOIC RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
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