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參數資料
| 型號： | AD7868AQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | LC2MOS Complete, 12-Bit Analog I/O System |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, CDIP24 |
| 封裝： | CERDIP-24 |
| 文件頁數： | 4/16頁 |
| 文件大小： | 337K |
| 代理商： | AD7868AQ |
AD7868
TIMNGCHARACTERISTICS
1, 2
–4–
REV. B
Limit at T
MIN
, T
MAX
(A, B Versions)
Limit at T
MIN
, T
MAX
(T Version)
Parameter
Units
Conditions/Comments
ADC T IMING
t
1
t
23
t
3
t
4
50
440
100
20
100
155
4
100
2 RCLK +200 to
3 RCLK + 200
50
440
100
20
100
155
4
100
2 RCLK +200 to
3 RCLK + 200
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns typ
CONVST
Pulse Width
RCLK Cycle T ime, Internal Clock
RFS
to RCLK Falling Edge Setup T ime
RCLK Rising Edge to
RFS
t
54
t
6
RCLK to Valid Data Delay, C
L
= 35 pF
Bus Relinquish T ime after RCLK
t
135
CONVST
to
RFS
Delay
DAC T IMING
t
7
t
8
t
96
t
10
t
11
t
12
50
75
150
30
75
40
50
100
200
40
100
40
ns min
ns min
ns min
ns min
ns min
ns min
TFS
to T CLK Falling Edge
T CLK Falling Edge to
TFS
T CLK Cycle T ime
Data Valid to T CLK Setup T ime
Data Valid to T CLK Hold T ime
LDAC
Pulse Width
NOT ES
1
T iming specifications are sample tested at +25
°
C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a
voltage level of 1.6 V.
2
Serial timing is measured with a 4.7 k
pull-up resistor on DR and
RFS
and a 2 k
pull-up resistor on RCLK . T he capacitance on all three output is 35 pF.
3
When using internal clock, RCLK mark/space ratio (measured from a voltage level of 1.6 V) range is 40/60 to 60/40. For external clock, RCLK mark/space ratio =
external clock mark/space ratio.
4
DR will drive higher capacitance loads but this will add to t
since it increases the external RC time constant (4.7 k
/C
L
) and hence the time to reach 2.4 V.
5
T ime 2 RCLK to 3 RCLK depends on conversion start to ADC clock synchronization.
6
T CLK mark/space ratio is 40/60 to 60/40.
WARNING!
ESD SENSITIVE DEVICE
C AUT ION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7868 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ABSOLUT E MAX IMUM RAT INGS*
(T
A
= +25
°
C unless otherwise noted)
V
DD
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
V
SS
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V
AGND to DGND . . . . . . . . . . . . . . . . . –0.3 V to V
DD
+0.3 V
V
OUT
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . V
SS
to V
DD
V
IN
to AGND . . . . . . . . . . . . . . . . V
SS
–0.3 V to V
DD
+ 0.3 V
RO ADC to AGND . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
RO DAC to AGND . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
RI DAC to AGND . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Digital Inputs to AGND . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Digital Outputs to AGND . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Operating T emperature Range
A, B Versions . . . . . . . . . . . . . . . . . . . . . . . –40
°
C to +85
°
C
T Version . . . . . . . . . . . . . . . . . . . . . . . . . –55
°
C to +125
°
C
Storage T emperature Range . . . . . . . . . . . . –65
°
C to +150
°
C
Lead T emperature (Soldering, 10 secs) . . . . . . . . . . . +300
°
C
Power Dissipation (Any Package) to +75
°
C . . . . . . . . 450 mW
Derates above +75
°
C by . . . . . . . . . . . . . . . . . . . . 10 mW/
°
C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. T his is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
DIP
RO ADC
DGND
TCLK
DT
RI DAC
AGND
CONTROL
CLK
RCLK
DR
DGND
AGND
RO DAC
NC
V
DD
NC = NO CONNECT
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
10
11
12
9
AD7868
TOP VIEW
(Not to Scale)
CONVST
RFS
V
SS
V
OUT
V
IN
TFS
LDAC
V
DD
V
SS
SOIC
RO ADC
DGND
TCLK
DT
RI DAC
AGND
CONTROL
CLK
RCLK
DR
DGND
AGND
RO DAC
NC
V
DD
NC = NO CONNECT
1
7
8
9
24
23
22
21
20
19
18
17
16
15
14
12
13
AD7868
TOP VIEW
(Not to Scale)
CONVST
RFS
V
SS
V
OUT
V
IN
TFS
LDAC
10
11
3
4
5
6
2
28
27
26
25
NC
NC
NC
NC
V
DD
V
SS
PIN CONFIGURAT IONS
(V
DD
= +5 V
6
5%, V
SS
= –5 V
6
5%, AGND = DGND = 0 V)
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