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參數(shù)資料
| 型號： | AD7868BN |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | LC2MOS Complete, 12-Bit Analog I/O System |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDIP24 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-24 |
| 文件頁數(shù)： | 7/16頁 |
| 文件大?。?/td> | 337K |
| 代理商： | AD7868BN |
AD7868
–7–
REV. B
500
200
100
50
20
10
50
100
200
1k
2k
10k
20k
100k
FREQUENCY – Hz
n
√
H
REF OUT
DAC OUTPUT
WITH ALL 0s
LOADED
REF OUT DECOUPLED
AS SHOWN IN
FIGURE 2
T
A
= +25
°
C
V
DD
= +5V
V
SS
= –5V
Figure 3. Noise Spectral Density vs. Frequency
INPUT /OUT PUT T RANSFE R FUNCT IONS
A bipolar circuit for the AD7868 is shown in Figure 4. T he ana-
log input/output voltage range of the AD7868 is
±
3 V. T he de-
signed code transitions for the ADC occur midway between
successive integer LSB values (i.e., 1/2 LSB, 3/2 LSB, 5/2 LSB
. . . FS – 3/2 LSBs). T he input/output code is 2s complement
binary with 1 LSB = FS/4096 = 1.46 mV. T he ideal transfer
function is shown in Figure 5.
AD7868*
RO ADC
RI DAC
AGND
*ADDITIONAL PINS OMITTED FOR CLARITY
V
IN
V
OUT
ANALOG OUTPUT
RANGE = ±3V
ANALOG INPUT
RANGE = ±3V
R1
200
C2
0.1μF
C1
10μF
Figure 4. AD7868 Basic Bipolar Operation Using RO ADC
as a Reference Input for the DAC
-FS
2
FS = 6V
1LSB =
FS
4096
0V
011...111
011...110
000...010
000...001
000...000
111...111
111...110
100...001
100...000
INPUT VOLTAGE
OUTPUT
CODE
2
-1LSB
FS
+
Figure 5. AD7868 Input/Output Transfer Function
OFFSE T AND FULL-SCALE ADJUST ME NT
In most digital signal processing (DSP) applications, offset and
full-scale errors have little or no effect on system performance.
Offset error can always be eliminated in the analog domain by
ac coupling. Full-scale errors do not cause problems as long as
the input signal is within the full dynamic range of the ADC. For
applications which require that the input signal range match the
full analog input dynamic range of the ADC, offset and full-scale
errors have to be adjusted to zero.
ADC ADJUST ME NT
Figure 6 has signal conditioning at the input and output of the
AD7868 for trimming the end points of the transfer functions of
both the ADC and the DAC. Offset error must be adjusted be-
fore full-scale error. For the ADC, this is achieved by trimming
the offset of A1 while the input voltage, V1, is 1/2 LSB below
ground. T he trim procedure is as follows: apply a voltage of
–0.73 mV (–1/2 LSB) at V1 in Figure 6 and adjust the offset
voltage of A1 until the ADC output code flickers between 1111
1111 1111 (FFF HEX ) and 0000 0000 0000 (000 HEX ).
ADC gain error can be adjusted at either the first code transi-
tion (ADC negative full scale) or the last code transition (ADC
positive full scale). T he trim procedures for both cases are as
follows (see Figure 6).
ADC Positive Full-Scale Adjustment
Apply a voltage of 2.9978 V (FS/2 – 3/2 LSBs) at V1. Adjust R2
until the ADC output code flickers between 0111 1111 1110
(7FE HEX ) and 0111 1111 1111 (7FF HEX ).
ADC Negative Full-Scale Adjustment
Apply a voltage of –2.9993 V (–FS/2 + 1/2 LSB) at V1 and
adjust R2 until the ADC output code flickers between 1000
0000 0000 (800 HEX ) and 1000 0000 0001 (801 HEX ).
DAC ADJUST ME NT
Op amp A2 is included in Figure 6 for the DAC transfer func-
tion adjustment. Again offset must be adjusted before full scale.
T o adjust offset: load the DAC with 0000 0000 0000 (000
HEX ) and trim the offset of A2 to 0 V. As with the ADC adjust-
ment, gain error can be adjusted at either the first code transi-
tion (DAC negative full scale) or the last code transition (DAC
positive full scale). T he trim procedures for both cases are as
follows:
DAC Positive Full-Scale Adjustment
Load the DAC with 0111 1111 1111 (7FF HEX ) and adjust R7
until the op amp output voltage is equal to 2.9985 V, (FS/2 –
1 LSB).
DAC Negative Full-Scale Adjustment
Load the DAC with 1000 0000 0000 (800 HEX ) and adjust R7
until the op amp output voltage is equal to 3.0 V (–FS/2).
AD7868*
*ADDITIONAL PINS
OMITTED FOR CLARITY
AGND
A1
V1
INPUT VOLTAGE
RANGE =
±
3V
R1
10k
R2
500
R3
10k
R5
10k
R4
10k
V
IN
V
OUT
A2
R6
10k
R7
500
R8
10k
R10
10k
R9
10k
V0
OUTPUT VOLTAGE
RANGE =
±
3V
Figure 6. AD7868 with Input/Output Adjustment
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD7868BQ | LC2MOS Complete, 12-Bit Analog I/O System |
| AD7868BR | LC2MOS Complete, 12-Bit Analog I/O System |
| AD7869AQ | LC2MOS Complete, 14-Bit Analog I/O System |
| AD7869JN | LC2MOS Complete, 14-Bit Analog I/O System |
| AD7869JR | LC2MOS Complete, 14-Bit Analog I/O System |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7868BNZ | 功能描述:IC I/O PORT 12BIT ANLG 24-DIP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
| AD7868BQ | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD7868BR | 制造商:Analog Devices 功能描述:Data Acquisition System Single ADC Single DAC 12-Bit 28-Pin SOIC W 制造商:Rochester Electronics LLC 功能描述:ANALOG I/O PORT IC - Bulk |
| AD7868BR-REEL | 功能描述:IC I/O PORT 12BIT ANLG 28-SOIC RoHS:否 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
| AD7868BRZ | 功能描述:IC I/O PORT 12BIT ANLG 28SOIC RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
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