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參數(shù)資料
| 型號： | AD7871JN |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | LC2MOS Complete 14-Bit, Sampling ADCs |
| 中文描述： | 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PDIP28 |
| 封裝： | PLASTIC, DIP-28 |
| 文件頁數(shù)： | 4/16頁 |
| 文件大小： | 344K |
| 代理商： | AD7871JN |
AD7871/AD7872
AD7871 PIN FUNCT ION DE SCRIPT ION
DIP
No.
Mnemonic
–4–
REV. D
Function
1
CONVST
Convert Start. A low to high transition on this input puts the track/hold into the hold mode. T his
input is asynchronous to the CLK .
CS
and
RD
must be held high for the duration of this pulse.
Chip Select. Active low logic input. T he device is selected when this input is active. With
CONVST
tied low, a new conversion is initiated when
CS
goes low.
Read. Active low logic input. T his input is used in conjunction with
CS
low to enable the data outputs.
Busy/Interrupt. Logic low output indicating converter status. See timing diagrams.
Clock Input. An external T T L-compatible clock may be applied to this input. Alternatively, tying
this pin to V
SS
enables the internal laser-trimmed oscillator.
Data Bit 13 (MSB)/High Byte Enable. T he function of this pin is dependent on the state of the
14/
8
/CLK input (see Pin 28). When 14-bit data is selected, this pin provides the DB13 output. When
either byte or serial data is selected, this pin becomes the HBEN logic input. HBEN is used for 8-bit
bus interfacing. When HBEN is low, DB7 to DB0 is the lower byte of data. With HBEN high, DB7
to DB0 is the upper byte of data (see T able I).
2
CS
3
4
5
RD
BUSY/INT
CLK
6
DB13/HBEN
T able I. Byte Output Format
HBEN DB7
HIGH
LOW
DB6 DB5 DB4 DB3
LOW LOW DB13 DB12 DB11 DB10 DB9 DB8
DB7
DB6 DB5 DB4 DB3
DB2
DB1 DB0
DB2
DB1 DB0
7
DB12/
SSTRB
Data Bit 12/Serial Strobe. When 14-bit data is selected, this pin provides the DB12 data output.
Otherwise it is an active low three-state output that provides a framing pulse for serial data.
Data Bit 11/Serial Clock. When 14-bit data is selected, this pin provides the DB11 data output.
Otherwise SCLK is the gated serial clock output that is derived from the internal or external ADC
clock. If the 14/
8
/CLK input is held at –5 V, then the SCLK runs continuously. With 14/
8
/CLK at
0 V, it is gated off (three-state) after serial transmission is complete.
Data Bit 10/Serial Data. When 14-bit parallel data is selected, this pin provides the DB10 data
output. Otherwise it is the three-state serial data output used in conjunction with SCLK and
SSTRB
in serial data transmission. Serial data is valid on the falling edge of SCLK , when
SSTRB
is low.
T hree-State Data Outputs controlled by
CS
and
RD
. T heir function depends on the state of the
14/
8
/CLK and the HBEN inputs. With 14/
8
/CLK high, they are always DB9–DB6; with 14/
8
/CLK
low, their function depends on HBEN (see T able I).
Digital Ground. Ground return for digital circuitry.
T hree-State Data Outputs controlled by
CS
and
RD
. T heir function depends on the 14/
8
/CLK
and HBEN inputs. With 14/
8
/CLK high, they are always DB5–DB0; with 14/
8
/CLK low or –5 V,
their function is controlled by HBEN (see T able I).
Positive Supply, +5 V
±
5%.
Analog Ground. Ground reference for analog circuitry.
Decoupling point for on-chip reference. Connect 10 nF between this pin and AGND.
No Connect.
Voltage Reference Output. T he internal 3 V reference is provided at this pin. T he external load
capability is 500
μ
A.
Analog Input. T he input range is
±
3 V.
Negative Supply, –5 V
±
5%.
T hree-Function Input. Defines both the parallel and serial data formats. With this pin at +5 V, the
output data is 14-bit parallel only. With this pin at 0 V, both byte and serial data are available, and
the SCLK is noncontinuous. With this pin at –5 V, both byte and serial data are available and the
SCLK is continuous.
8
DB11/SCLK
9
DB10/SDAT A
10–13 DB9–DB6
14
15–20 DB5/DB13–
DB0/DB8
DGND
21
22
23
24
25
V
DD
AGND
C
REF
NC
REF OUT
26
27
28
V
IN
V
SS
14/
8
/CLK
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