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參數資料
| 型號： | AD7875CQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | LC2MOS Complete, 12-Bit, 100 kHz, Sampling ADCs |
| 中文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CDIP24 |
| 封裝： | 0.300 INCH, HERMETIC SEALED, CERAMIC, DIP-24 |
| 文件頁數： | 10/20頁 |
| 文件大小： | 331K |
| 代理商： | AD7875CQ |
REV. B
AD7870/AD7875/AD7876
–10–
Figure 10. Mode 1 Timing Diagram, Byte or Serial Read
its
BUSY
function.
BUSY
goes low at the start of conversion,
stays low during the conversion and returns high when the con-
version is complete. It is normally used in parallel interfaces to
drive the microprocessor into a WAIT state for the duration of
conversion.
Figure 11 shows the Mode 2 timing diagram for the 12-bit par-
allel data output format (12/
8
/CLK = +5 V). In this case, the
ADC behaves like slow memory. T he major advantage of this
interface is that it allows the microprocessor to start conversion,
WAIT and then read data with a single READ instruction. T he
user does not have to worry about servicing interrupts or ensur-
ing that software delays are long enough to avoid reading during
conversion.
Figure 11. Mode 2 Timing Diagram, 12-Bit Parallel Read
T he Mode 1 timing diagram for byte and serial data is shown in
Figure 10.
INT
goes low at the end of conversion and is reset
high by the first falling edge of
CS
and
RD
. T his first read at the
end of conversion can either access the low byte or high byte of
data depending on the status of HBEN (Figure 10 shows low
byte only for example). T he diagram shows both a noncontinu-
ously and a continuously running clock (dashed line).
MODE 2 INT E RFACE
T he second interface mode is achieved by hard wiring
CONVST
low and conversion is initiated by taking
CS
low while HBEN is
low. T he track/hold amplifier goes into the hold mode on the
falling edge of
CS
. In this mode, the
BUSY
/
INT
pin assumes
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