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參數(shù)資料
| 型號(hào)： | AD7878AQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | LC2MOS Complete 12-Bit 100 kHz Sampling ADC with DSP Interface |
| 中文描述： | 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CDIP28 |
| 封裝： | HERMETIC SEALED, CERDIP-28 |
| 文件頁數(shù)： | 2/16頁 |
| 文件大小： | 417K |
| 代理商： | AD7878AQ |
AD7878–SPECIFICATIONS
–2–
REV. A
(V
DD
= +5 V
6
5%, V
CC
= +5 V
6
5%, V
SS
= –5 V
6
5%, AGND = DGND =
0 V, f
CLK
= 8 MHz. All Specifications T
MIN
to T
MAX
, unless otherwise noted.)
J, A
Versions
1
Versions Version
K, L, B
S
Parameter
Units
Test Conditions/Comments
DYNAMIC PERFORMANCE
2
Signal-to-Noise Ratio (SNR)
3
@ 25
°
C
T
MIN
to T
MAX
Total Harmonic Distortion (THD)
70
70
–80
72
71
–80
70
70
–78
dB min
dB min
dB max
V
IN
= 10 kHz Sine Wave, f
SAMPLE
= 100 kHz
Typically 71.5 dB for 0 < V
IN
< 50 kHz
V
IN
= 10 kHz Sine Wave, f
SAMPLE
= 100 kHz
Typically –86 dB for 0 < V
IN
< 50 kHz
V
IN
= 10 kHz, f
SAMPLE
= 100 kHz
Typically –86 dB for 0 < V
IN
< 50 kHz
Peak Harmonic or Spurious Noise
–80
–80
–78
dB max
Intermodulation Distortion (IMD)
Second Order Terms
Third Order Terms
Track/Hold Acquisition Time
DC ACCURACY
Resolution
Minimum Resolution for Which
No Missing Codes are Guaranteed
Relative Accuracy
Differential Nonlinearity
Bipolar Zero Error
Positive Full-Scale Error
4
Negative Full-Scale Error
4
ANALOG INPUT
Input Voltage Range
Input Current
REFERENCE OUTPUT
5
REF OUT
REF OUT Error @ 25
°
C
T
MIN
to T
MAX
Reference Load Sensitivity
(
REF OUT/
I)
–80
–80
2
–80
–80
2
–78
–78
2
dB max
dB max
μ
s max
fa = 9 kHz, fb = 9.5 kHz, f
SAMPLE
= 50 kHz
fa = 9 kHz, fb = 9.5 kHz, f
SAMPLE
= 50 kHz
See Throughput Rate Section
12
12
12
Bits
12
±
1/2
±
1/2
±
6
±
6
±
6
12
±
1/4
±
1/2
±
6
±
6
±
6
12
±
1/2
±
1/2
±
6
±
6
±
6
Bits
LSB typ
LSB typ
LSB max
LSB max
LSB max
±
3
±
550
±
3
±
550
±
3
±
550
Volts
μ
A max
3
±
10
±
15
3
±
10
±
15
3
±
10
±
15
V nom
mV max
mV max
±
1
±
1
±
1
mV max
Reference Load Current Change (0
μ
A–500
μ
A).
Reference Load Should Not Be Changed
During Conversion
LOGIC INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
Input Capacitance, C
IN6
LOGIC OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
DB11–DB0
Floating State Leakage Current
Floating State Output Capacitance
6
CONVERSION TIME
+2.4
+0.8
±
10
10
+2.4
+0.8
±
10
10
+2.4
+0.8
±
10
10
V min
V max
μ
A max
pF max
V
CC
= +5 V
±
5%
V
CC
= +5 V
±
5%
V
IN
= 0 to V
CC
+2.7
+0.4
+2.7
+0.4
+2.7
+0.4
V min
V max
I
SOURCE
40
μ
A
I
SINK
= 1.6 mA
±
10
15
±
10
15
±
10
15
±
10
15
μ
A max
pF max
7/7.125
7/9.250
7/7.125
7/9.250
7/7.125
7/9.250
μ
s min/
μ
s max
μ
s min/
μ
s max
Assuming No External Read/Write Operations
Assuming 17 External Read/Write Operations
See Internal Comparator Timing Section
POWER REQUIREMENTS
V
DD
V
CC
V
SS
I
DD
I
CC
I
SS
Power Dissipation
+5
+5
–5
13
100
6
95.5
+5
+5
–5
13
100
6
95.5
+5
+5
–5
13
100
6
95.5
V nom
V nom
V nom
mA max
μ
A max
mA max
mW max
±
5% for Specified Performance
±
5% for Specified Performance
±
5% for Specified Performance
CS
=
DMWR
=
DMRD
= 5 V
CS
=
DMWR
=
DMRD
= 5 V
CS
=
DMWR
=
DMRD
= 5 V
Typically 60 mW
NOTES
1
Temperature range as follows: J, K, L versions: 0
°
C to +70
°
C; A, B versions: –25
°
C to +85
°
C; S version: –55
°
C to +125
°
C.
2
V
=
±
3 V. See Dynamic Specifications section.
3
SNR calculation includes distortion and noise components.
4
Measured with respect to the Internal Reference.
5
For capacitive loads greater than 50 pF a series resistor is required (see Internal Reference section).
6
Sample tested @ +25
°
C to ensure compliance.
Specifications subject to change without notice.
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