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參數資料
型號: AD7880
廠商: Analog Devices, Inc.
英文描述: Enclosed Switches Series LS: Rod - Adjustable; 1NC 1NO DPDT Snap Action, Double Break; 0.5 in - 14NPT conduit; Plug-in
中文描述: LC2MOS單5伏電源,低功耗,12位采樣ADC
文件頁數: 5/16頁
文件大小: 337K
代理商: AD7880
AD7880
REV. 0
–5–
+
R
V
INA
V
INB
R
V
DAC
Figure 4. AD7880 Input Circuit
T he AD7880 accommodates three separate input ranges, 0 to
V
REF
, 0 to 2 V
REF
and
±
V
REF
. T he input configurations corre-
sponding to these ranges are shown in Figures 5, 6 and 7.
With V
REF
= V
DD
and using a nominal V
DD
of +5 V, the input
ranges are 0 V to 5 V, 0 V to 10 V and +5 V, as shown in
T able II.
T able II. Analog Input Ranges
Analog Input
Range
Input Connections
V
INA
Connection
Diagram
V
RE F
V
INB
0 V to +5 V
0 V to +10 V
±
5 V
V
DD
V
DD
V
DD
V
IN
V
IN
V
IN
V
IN
AGND
V
REF
Figure 5
Figure 6
Figure 7
+
R
R
SAMPLING
COMPARATOR
V
INA
V
INB
V
REF
AGND
12-BIT DAC
0 TO V
REF
V
REF
= 0 TO V
REF
V
IN
Figure 5. 0 to V
REF
Unipolar Input Configuration
+
R
R
SAMPLING
COMPARATOR
V
INA
V
INB
V
REF
AGND
12-BIT DAC
0 TO V
REF
V
REF
= 0 TO 2V
REF
V
IN
Figure 6. 0 to 2 V
REF
Unipolar Input Configuration
+
R
R
SAMPLING
COMPARATOR
V
INA
V
INB
V
REF
AGND
12-BIT DAC
0 TO V
REF
V
REF
= V
REF
±
V
IN
Figure 7.
±
V
REF
Bipolar Input Configuration
CIRCUIT INFORMAT ION
T he AD7880 is a +5 V single supply 12-bit A/D converter. T he
part requires no external components apart from a 2.5 MHz ex-
ternal clock and power supply decoupling capacitors. It contains
a 12-bit successive approximation ADC based on a fast-settling
voltage-output DAC, a high speed comparator and SAR, as well
as the necessary control logic. T he charge balancing comparator
used in the AD7880 provides the user with an inherent track-
and-hold function. T he ADC is specified to work with sampling
rates up to 66 kHz.
CONVE RT E R DE T AILS
T he AD7880 conversion cycle is initiated on the rising edge of
the CONVST pulse, as shown in the timing diagram of Figure
1. T he rising edge of the
CONVST
pulse places the track/hold
amplifier into “HOLD” mode. T he conversion cycle then takes
between 26 and 28 clock periods. T he maximum specified con-
version time is 12
μ
s. T his corresponds to a conversion cycle
time of 28 clock periods with a CLK IN frequency of 2.5 MHz
and also includes internal propagation delays. During conver-
sion the
BUSY
output will remain low, and the output databus
drivers will be three-stated. When a conversion is completed,
the
BUSY
output will go to a high level, and the result of the
conversion can be read by bringing
CS
and
RD
low.
T he track/hold amplifier acquires a 12-bit input signal in 3
μ
s.
T he overall throughput time for the AD7880 is equal to the
conversion time plus the track/hold acquisition time. For a
2.5 MHz input clock the throughput time is 15
μ
s.
RE FE RE NCE INPUT
For specified performance, it is recommended that the reference
input be tied to V
DD
. T he part, however, will operate with a ref-
erence down to 2.5 V though with reduced performance specifi-
cations. Figure 3 shows a graph of signal-to-noise ratio (SNR)
versus V
REF
.
V
REF
must not be allowed to go above V
DD
by more than
100 mV.
74
72
70
68
66
64
62
602
3
4
5
V
REF
– Volts
S
F = 51.2kHz
F = 2.525kHz
T = 25 C
Figure 3. SNR vs. V
REF
ANALOG INPUT
T he AD7880 has two analog input pins, V
INA
and V
INB
. Figure
4 shows the input circuitry to the ADC sampling comparator.
T he on-board attenuator network, made up of equal resistors,
allows for various input ranges.
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AD7880CR LC2MOS Single +5 V Supply, Low Power, 12-Bit Sampling ADC
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