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參數資料
| 型號： | AD7884BN |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | LC2MOS 16-Bit, High Speed Sampling ADCs |
| 中文描述： | 1-CH 16-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數： | 9/16頁 |
| 文件大小： | 319K |
| 代理商： | AD7884BN |
AD7884/AD7885
REV. C
–9–
T iming and Control Section
Figure 9 shows the timing and control sequence for the
AD7884/AD7885. When the part receives a
CONVST
pulse,
the conversion begins. T he input sample-and-hold goes into the
hold mode 50 ns after the rising edge of
CONVST
and
BUSY
goes low. T his is the first phase of conversion and takes 3.35
μ
s
to complete. T he second phase of conversion begins when SW2
is turned off and SW3 turned on. T he Residue Amplifier and
SHA section (A2 in Figure 8) goes into hold mode at this point
and allows the input sample-and-hold to go back into sample
mode. T hus, while the second phase of conversion is ongoing,
the input sample-and-hold is also acquiring the input signal for
the next conversion. T his overlap between conversion and ac-
quisition allows throughput rates of 166 kSPS to be achieved.
CONVST
BUSY
SAMPLE
HOLD
INPUT
SHA
FIRST PHASE
3.5
μ
s
TACQ
2.5
μ
s
SECOND
PHASE
FIRST PHASE OF CONVERSION
1ST 9-BIT CONVERSION
DAC SETTLING TIME
RESIDUE AMPLIFIER
SETTLING TIME
SECOND PHASE OF CONVERSION
2ND 9-BIT CONVERSION
ERROR CORRECTION
OUTPUT LATCH UPDATE
1.8
μ
s
Figure 9. Timing and Control Sequence
USING T HE AD7884/AD7885 ANALOG INPUT RANGE S
T he AD7884/AD7885 can be set up to have either a
±
3 volts
analog input range or a
±
5 volts analog input range. Figures 10
and 11 show the necessary corrections for each of these. T he
output code is 2s complement and the ideal code table for both
input ranges is shown in T able I.
Reference Considerations
T h
e
AD7884/AD7885 operates from a
±
3 volt reference. T his
can be derived simply using the AD780 as shown in Figure 6.
A1
V
INV
±
3V S
±
3V F
±
5V S
±
5V F
Figure 10.
±
5 V Input Range Connection
±
3V S
±
3V F
±
5V S
±
5V F
A1
V
INV
Figure 11.
±
3 V Input Range Connections
T he critical performance specification for a reference in a 16-bit
application is noise. T he reference pk-pk noise should be insig-
nificant in comparison to the ADC noise. T he AD7884/
AD7885 has a typical rms noise of 120
μ
V. For example a rea-
sonable target would be to keep the total rms noise less than
125
μ
V. T o do this the reference noise needs to be less than
35
μ
V rms. In the 100 kHz band, the AD780 noise is less than
30
μ
V rms, making it a very suitable reference.
T he buffer amplifier used to drive the device V
REF+
should have
low enough noise performance so as not to affect the overall
system noise requirement. T he AD845 and AD817 achieve
this.
T able I. Ideal Output Code T able for the AD7884/AD7885
Analog Input
6
3 V Range
3
Digital Output
Code T ransition
l
In T erms of FSR
2
6
5 V Range
4
+FSR/2 – 1 LSB
+FSR/2 – 2 LSBs
+FSR/2 – 3 LSBs
AGND + 1 LSB
AGND
AGND – 1 LSB
–(FSR/2 – 3 LSBs)
–(FSR/2 – 2 LSBs)
–(FSR/2 – 1 LSB)
2.999908
2.999817
2.999726
0.000092
0.000000
–0.000092
–2.999726
–2.999817
–2.999908
4.999847
4.999695
4.999543
0.000153
0.000000
–0.000153
–4.999543
–4.999695
–4.999847
011 . . . 111 to 111 . . . 110
011 . . . 110 to 011 . . . 101
011 . . . 101 to 011 . . . 100
000 . . . 001 to 000 . . . 000
000 . . . 000 to 111 . . . 111
111 . . . 111 to 111 . . . 110
100 . . . 011 to 100 . . . 010
100 . . . 010 to 100 . . . 001
100 . . . 001 to 100 . . . 000
NOT ES
1
T his table applies for V
S = +3 V.
2
FSR (Full-Scale Range) is 6 volts for the
±
3 V input range and 10 volts for the
±
5 V input range.
3
1 LSB on the
±
3 V range is FSR/2
16
and is equal to 91.5
μ
V.
4
1 LSB on the
±
5 V range is FSR/2
16
and is equal to 152.6
μ
V.
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