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參數(shù)資料
| 型號： | AD7892BR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Dual High Efficiency, Low Noise, Synchronous Step-Down Switching Regulators |
| 中文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PDSO24 |
| 封裝： | SOIC-24 |
| 文件頁數(shù)： | 7/14頁 |
| 文件大小： | 144K |
| 代理商： | AD7892BR |
AD7892
REV. C
–7–
Pin
No.
Mnemonic
Description
16
DB4/SCLK
Data Bit 4/Serial Clock. When the device is in its parallel mode, this pin is Data Bit 4, a three-state
TTL-compatible output. When the device is in its serial mode, this becomes the serial clock pin,
SCLK. SCLK is an input and an external serial clock must be provided at this pin to obtain serial
data from the AD7892. Serial data is clocked out from the output shift register on the rising edges
of SCLK after
RFS
goes low.
Data Bit 3/Receive Frame Synchronization. When the device is in its parallel mode, this pin is Data
Bit 3, a three-state TTL-compatible output. When the device is in its serial mode, this becomes the
receive frame synchronization input with
RFS
provided externally to obtain serial data from the
AD7892.
Data Bit 2. Three-state TTL-compatible output. This output should be left unconnected when the
device is in its serial mode.
Data Bit 1. Three-state TTL-compatible output. This output should be left unconnected when the
device is in its serial mode.
Data Bit 0 (LSB). Three-state TTL-compatible output. Output coding is two’s complement for
AD7892-1 and AD7892-3 and straight (natural) binary for AD7892-2. This output should be left
unconnected when the device is in its serial mode.
Read. Active low logic input which is used in conjunction with
CS
low to enable the data outputs.
Chip Select. Active low logic input which is used in conjunction with
RD
to enable the data outputs.
End-of-Conversion. Active low logic output indicating converter status. The end of conversion is
signified by a low going pulse on this line. The duration of this
EOC
pulse is nominally 100 ns.
Convert Start. Logic Input. A low-to-high transition on this input puts the track/hold into its hold
mode and starts conversion.
17
DB3/
RFS
18
DB2
19
DB1
20
DB0
21
22
23
RD
CS
EOC
24
CONVST
PIN CONFIGURATION
DIP and SOIC
V
DD
REF OUT/REF IN
AGND
MODE
DB0 (LSB)
DB1
DB2
V
IN2
V
IN1
DB11/LOW
DB3/
RFS
DB10/LOW
DB4/SCLK
DB9
DB5/SDATA
DB8
DGND
DB7
DB6
14
1
2
24
23
5
6
7
20
19
18
3
4
22
21
8
17
9
16
10
15
11
TOP VIEW
(Not to Scale)
12
13
AD7892
STANDBY
CONVST
EOC
CS
RD
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PDF描述 |
|---|---|
| AD7892SQ | Dual High Efficiency, Low Noise, Synchronous Step-Down Switching Regulators |
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| AD7892AN-2 | LC2MOS Single Supply, 12-Bit 600 kSPS ADC |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7892BR-1 | 功能描述:IC ADC 12BIT 5V 500KSPS 24-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個(gè)單端，雙極 |
| AD7892BR-1REEL | 功能描述:IC ADC 12BIT LP 500KSPS 24-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個(gè)單端，雙極 |
| AD7892BR-1Z | 制造商:Analog Devices 功能描述:ADC 12BIT 500KSPS 1LSB 24S 制造商:Analog Devices 功能描述:ADC, 12BIT, 500KSPS, 1LSB, 24SOIC; Resolution (Bits):12bit; Sampling Rate:500kSPS; Supply Voltage Type:Single; Supply Voltage Min:4.75V; Supply Voltage Max:5.25V; Supply Current:18mA; Digital IC Case Style:SOIC; No. of Pins:24; Input;RoHS Compliant: Yes |
| AD7892BR-2 | 制造商:Rochester Electronics LLC 功能描述:12-BIT 500 KSPS PARALLEL ADC I.C. - Bulk |
| AD7892BR-2REEL | 制造商:Analog Devices 功能描述:ADC Single SAR 500ksps 12-bit Parallel/Serial 24-Pin SOIC W T/R |
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