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參數資料
| 型號： | AD7892SQ-1 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | LC2MOS Single Supply, 12-Bit 600 kSPS ADC |
| 中文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CDIP24 |
| 封裝： | 0.300 INCH, HERMETIC SEALED, CERDIP-24 |
| 文件頁數： | 4/14頁 |
| 文件大小： | 144K |
| 代理商： | AD7892SQ-1 |
AD7892
TIMING CHARACTERISTICS
1, 2
–4–
REV. C
A, B
Versions
S
Version
Parameter
Unit
μ
s max
μ
s max
ns min
ns min
Test Conditions/Comments
t
CONV
1.47
1.6
200
400
Conversion Time for AD7892-3
Conversion Time for AD7892-1, AD7892-2
Acquisition Time for AD7892-3
Acquisition Time for AD7892-1, AD7892-2
1.68
t
ACQ
320
Parallel Interface
t
1
t
2
t
3
t
4
t
5
t
63
t
74
35
60
0
0
35
35
5
30
0
200
45
60
0
0
45
40
5
40
0
200
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns min
CONVST
Pulsewidth
EOC
Pulsewidth
EOC
Falling Edge to
CS
Falling Edge Setup Time
CS
to
RD
Setup Time
Read Pulsewidth
Data Access Time After Falling Edge of
RD
Bus Relinquish Time After Rising Edge of
RD
t
8
t
9
Serial Interface
t
10
t
113
t
12
t
13
t
143
t
153
t
16
t
174
CS
to
RD
Hold Time
RD
to
CONVST
Setup Time
30
25
25
25
5
25
20
0
30
0
30
35
30
25
25
5
30
30
0
30
0
30
ns min
ns max
ns min
ns min
ns min
ns max
ns min
ns min
ns max
ns min
ns max
RFS
Low to SCLK Falling Edge Setup Time
RFS
Low to Data Valid Delay
SCLK High Pulsewidth
SCLK Low Pulsewidth
SCLK Rising Edge to Data Valid Hold Time
SCLK Rising Edge to Data Valid Delay
RFS
to SCLK Falling Edge Hold Time
Bus Relinquish Time after Rising Edge of
RFS
t
17A4
Bus Relinquish Time after Rising Edge of SCLK
NOTES
1
Sample tested at +25
°
C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of +5 V) and timed from a voltage level of +1.6 V.
2
See Figures 2 and 3.
3
Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
4
These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
5
Assumes CMOS loads on the data bits. With TTL loads, more current is drawn from the data lines and the
RD
to
CONVST
time needs to be extended to 400 ns min.
Specifications subject to change without notice.
1.6mA
+1.6V
200 A
50pF
TO
OUTPUT
PIN
Figure 1. Load Circuit for Access Time and Bus Relinquish Time
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7892 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
(V
DD
= +5 V 5%, AGND = DGND = 0 V, REF IN = +2.5 V)
WARNING!
ESD SENSITIVE DEVICE
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