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參數(shù)資料
| 型號(hào)： | AD7896AR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 2.7 V to 5.5 V, 12-Bit, 8 us ADC in 8-Pin SO/DIP |
| 中文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
| 封裝： | MS-012AA, SOIC-8 |
| 文件頁數(shù)： | 4/12頁 |
| 文件大小： | 367K |
| 代理商： | AD7896AR |
REV. B
–4–
AD7896
PIN FUNCTION DESCRIPTION
Pin
No.
Pin
Mnemonic
Description
1
2
3
4
V
IN
V
DD
AGND
SCLK
Analog Input. The analog input range is 0 V to V
DD
.
Positive supply voltage, +2.7 V to 5.5 V.
Analog Ground. Ground reference for track/hold, comparator and DAC.
Serial Clock Input. An external serial clock is applied to this input to obtain serial data from
the AD7896. A new serial data bit is clocked out on the falling edge of this serial clock. Data
is guaranteed valid for 10 ns after this falling edge so data can be accepted on the falling edge
when a fast serial clock is used. The serial clock input should be taken low at the end of the
serial data transmission.
Serial Data Output. Serial data from the AD7896 is provided at this output. The serial data
is clocked out by the falling edge of SCLK, but the data can also be read on the falling edge
of the SCLK. This is possible because data bit N is valid for a specified time after the falling
edge of the SCLK (data hold time) and can be read before data bit N+1 becomes valid a
specified time after the falling edge of SCLK (data access time) (see Figure 4). Sixteen bits
of serial data are provided with four leading zeros followed by the 12 bits of conversion data.
On the sixteenth falling edge of SCLK, the SDATA line is held for the data hold time and
then disabled (three-stated). Output data coding is straight binary.
Digital Ground. Ground reference for digital circuitry.
Convert Start. Edge-triggered logic input. On the falling edge of this input, the track/hold
goes into its hold mode and conversion is initiated. If
CONVST
is low at the end of conver-
sion, the part goes into power down mode. In this case, the rising edge of
CONVST
“wakes up” the part.
The BUSY pin is used to indicate when the part is doing a conversion. The BUSY pin will go
high on the falling edge of
CONVST
and will return low when the conversion is complete.
5
SDATA
6
7
DGND
CONVST
8
BUSY
PIN CONFIGURATION
1
2
3
4
8
7
6
5
TOP VIEW
(Not to Scale)
AD7896
V
IN
SDATA
DGND
CONVST
BUSY
V
DD
AGND
SCLK
ORDERING GUIDE
Temperature
Range
Linearity
Error (LSB)
SNR
(dB)
Package
Option*
Model
AD7896AN
AD7896BN
AD7896AR
AD7896BR
AD7896JR
AD7896SQ
–40
°
C to +85
°
C
–40
°
C to +85
°
C
–40
°
C to +85
°
C
–40
°
C to +85
°
C
0
°
C to +70
°
C
–55
°
C to +125
°
C
±
1 LSB
±
1/2 LSB
±
1 LSB
±
1/2 LSB
±
1 LSB
±
1 LSB
70 dB
70 dB
70 dB
70 dB
70 dB
70 dB
N-8
N-8
SO-8
SO-8
SO-8
Q-8
*N = Plastic DIP; Q = Cerdip; SO = SOIC.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD7896BN | 2.7 V to 5.5 V, 12-Bit, 8 us ADC in 8-Pin SO/DIP |
| AD7896BR | 2.7 V to 5.5 V, 12-Bit, 8 us ADC in 8-Pin SO/DIP |
| AD7896SQ | 2.7 V to 5.5 V, 12-Bit, 8 us ADC in 8-Pin SO/DIP |
| AD7896* | Parallel Input, 12-Bit Rail-to-Rail Micropower DACs in SSOP; Package: PDIP; No of Pins: 24; Temperature Range: -40°C to +85°C |
| AD7898 | 5 V, 12-Bit, Serial 220 kSPS ADC in an 8-Lead Package |
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