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參數資料
| 型號： | AD7911ARM-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 2-Channel, 2.35 V to 5.25 V 250 kSPS, 10-/12-Bit ADCs |
| 中文描述： | 2-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
| 封裝： | MO-187AA, MSOP-8 |
| 文件頁數： | 22/28頁 |
| 文件大小： | 312K |
| 代理商： | AD7911ARM-REEL7 |
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AD7911/AD7921
MICROPROCESSOR INTERFACING
The serial interface on the AD7911/AD7921 allows the parts to
be directly connected to a range of microprocessors. This
section explains how to interface the AD7911/AD7921 with
some of the more common microcontroller and DSP serial
interface protocols.
AD7911/AD7921 to TMS320C541 Interface
The serial interface on the TMS320C541 uses a continuous
serial clock and frame synchronization signals to synchronize
the data transfer operations with peripheral devices like the
AD7911/AD7921. The CS input allows easy interfacing between
the TMS320C541 and the AD7911/AD7921 without any glue
logic required. The serial port of the TMS320C541 is set up to
operate in burst mode (FSM = 1 in the serial port control
register, SPC) with the internal serial clock CLKX (MCM = 1 in
the SPC register) and the internal frame signal (TXM = 1 in the
SPC register); therefore, both pins are configured as outputs. For
the AD7921, the word length should be set to 16 bits (FO = 0 in
the SPC register). This DSP allows frames with a word length of
16 bits or 8 bits only. In the AD7911, therefore, where 14 bits are
required, the FO bit should be set up to 16 bits, and 16 SCLKs
are needed. For the AD7911, two trailing zeros are clocked out
in the last two clock cycles.
Rev. 0 | Page 22 of 28
The values in the SPC register are as follows:
FO = 0
FSM = 1
MCM = 1
TXM = 1
To implement the power-down mode on the AD7911/AD7921,
the format bit, FO, can be set to 1, which sets the word length to
8 bits.
The connection diagram is shown in Figure 32. Note that, for
signal processing applications, the frame synchronization signal
from the TMS320C541 must provide equidistant sampling.
AD7911/
AD7921*
TMS320C541*
CLKX
DR
DX
FSX
FSR
SCLK
DOUT
DIN
CS
CLKR
0
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 32. Interfacing to the TMS320C541
AD7911/AD7921 to ADSP-218x
The ADSP-218x family of DSPs are interfaced directly to the
AD7911/AD7921 without any glue logic required. The SPORT
control register should be set up as follows:
TFSW = RFSW = 1, alternate framing
INVRFS = INVTFS = 1, active low frame signal
DTYPE = 00, right-justify data
ISCLK = 1, internal serial clock
TFSR = RFSR = 1, frame every word
IRFS = 0, set up RFS as an input
ITFS = 1, set up TFS as an output
SLEN = 1111, 16 bits for the AD7921
SLEN = 1101, 14 bits for the AD7911
To implement the power-down mode, SLEN should be set to
0111 to issue an 8-bit SCLK burst. The connection diagram is
shown in Figure 33. The ADSP-218x has the TFS and RFS of the
SPORT tied together, with TFS set as an output and RFS set as
an input. The DSP operates in alternate framing mode and the
SPORT control register is set up as described previously. The
frame synchronization signal generated on the TFS is tied to CS
and, as with all signal processing applications, equidistant
sampling is necessary. However, in this example, the timer
interrupt is used to control the sampling rate of the ADC and,
under certain conditions, equidistant sampling might not be
achieved.
AD7911/
AD7921*
ADSP-218x*
SCLK
RFS
TFS
SCLK
CS
DR
DOUT
DT
DIN
0
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 33. Interfacing to the ADSP-218x
The timer registers are loaded with a value that provides an
interrupt at the required sample interval. When an interrupt is
received, a value is transmitted with TFS/DT (ADC control
word). The TFS is used to control the RFS and, therefore, the
reading of data. The frequency of the serial clock is set in the
SCLKDIV register. When the instruction to transmit with TFS
is given, that is, TX0 = AX0, the state of the SCLK is checked.
The DSP waits until the SCLK has gone high, low, and high
again before transmission starts. If the timer and SCLK values
are chosen such that the instruction to transmit occurs on or
near the rising edge of SCLK, the data might be transmitted, or
it might wait until the next clock edge.
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