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參數(shù)資料
| 型號： | AD7918BRU-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 8-Channel, 1 MSPS, 8-/10-/12-Bit ADCs with Sequencer in 20-Lead TSSOP |
| 中文描述： | 8-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| 封裝： | MO-153AC, TSSOP-20 |
| 文件頁數(shù)： | 8/24頁 |
| 文件大?。?/td> | 607K |
| 代理商： | AD7918BRU-REEL7 |
AD7908/AD7918/AD7928
TIMING SPECIFICATIONS
1
REV. A
(AV
DD
= 2.7 V to 5.25 V, V
DRIVE
< AV
DD
, REF
IN
= 2.5 V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
Limit at T
MIN
, T
MAX
AD7908/AD7918/AD7928
AV
DD
= 3 V
AV
DD
= 5 V
10
10
20
20
16 t
SCLK
16 t
SCLK
50
50
Parameter
f
SCLK2
Unit
Description
kHz min
MHz max
t
CONVERT
t
QUIET
ns min
Minimum Quiet Time Required between
CS
Rising Edge
and Start of Next Conversion
CS
to SCLK Setup Time
Delay from
CS
until DOUT Three-State Disabled
Data Access Time after SCLK Falling Edge
SCLK Low Pulse Width
SCLK High Pulse Width
SCLK to DOUT Valid Hold Time
SCLK Falling Edge to DOUT High Impedance
DIN Setup Time Prior to SCLK Falling Edge
DIN Hold Time after SCLK Falling Edge
Sixteenth SCLK Falling Edge to
CS
High
Power-Up Time from Full Power-Down/Auto Shutdown Mode
t
2
t
33
t
43
t
5
t
6
t
7
t
84
t
9
t
10
t
11
t
12
10
35
40
0.4 t
SCLK
0.4 t
SCLK
10
15/45
10
5
20
1
10
30
40
0.4 t
SCLK
0.4 t
SCLK
10
15/35
10
5
20
1
ns min
ns max
ns max
ns min
ns min
ns min
ns min/max
ns min
ns min
ns min
μs max
NOTES
1
Sample tested at 25
°
C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of AV
) and timed from a voltage level of 1.6 V.
See Figure 1. The 3 V operating range spans from 2.7 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V.
2
Mark/Space ratio for the SCLK input is 40/60 to 60/40.
3
Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.4 V or 0.7
4
t
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time
, t
8
, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
Specifications subject to change without notice.
V
.
TO
OUTPUT
PIN
C
L
50pF
200 A
I
OH
200 A
I
OL
1.6V
Figure 1. Load Circuit for Digital Output Timing Specifications
–8–
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