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參數資料
| 型號： | AD7920BKS-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 250 kSPS, 10-/12-Bit ADCs in 6-Lead SC70 |
| 中文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO6 |
| 封裝： | MO-203AB, SC-70, 6 PIN |
| 文件頁數： | 13/20頁 |
| 文件大?。?/td> | 1091K |
| 代理商： | AD7920BKS-REEL7 |
REV. B
AD7910/AD7920
–13–
Power-Down Mode
This mode is intended for use in applications where slower through-
put rates are required; either the ADC is powered down between
conversions, or a series of conversions may be performed at a
high throughput rate and the ADC is powered down for a rela-
tively long duration between these bursts of several conversions.
When the AD7910/AD7920 is in power-down mode, all analog
circuitry is powered down.
To enter power-down mode, the conversion process must be
interrupted by bringing
CS
high anywhere after the second
falling edge of SCLK, and before the 10th falling edge of SCLK
as shown in Figure 10. Once
CS
has been brought high in this
window of SCLKs, the part will enter power-down mode, the
conversion that was initiated by the falling edge of
CS
will be
terminated, and SDATA will go back into three-state. If
CS
is
brought high before the second SCLK falling edge, the part will
remain in Normal mode and will not power down. This will
avoid accidental power-down due to glitches on the
CS
line.
To exit this mode of operation and power up the AD7910/AD7920
again, a dummy conversion is performed. On the falling edge of
CS
,
the device will begin to power up, and will continue to power up
as long as
CS
is held low until after the falling edge of the 10th
SCLK. The device will be fully powered up once 16 SCLKs
have elapsed and valid data will result from the next conversion,
as shown in Figure 11. If
CS
is brought high before the 10th SCLK
falling edge, the AD7910/AD7920 will go back into power-down
mode again. This avoids accidental power-up due to glitches on
the
CS
line or an inadvertent burst of eight SCLK cycles while
CS
is low. Although the device may begin to power up on the
falling edge of
CS
, it will power down again on the rising edge
of
CS
as long as it occurs before the 10th SCLK falling edge.
Power-Up Time
The power-up time of the AD7910/AD7920 is 1
m
s, which means
that one dummy cycle will always be sufficient to allow the device
to power up. Once the dummy cycle is complete, the ADC will
be fully powered up and the input signal will be acquired properly.
The quiet time, t
QUIET
, must still be allowed from the point where
the bus goes back into three-state after the dummy conversion,
to the next falling edge of
CS
.
When powering up from the power-down mode with a dummy
cycle, as in Figure 11, the track-and-hold that was in hold mode
while the part was powered down returns to track mode after
VALID DATA
SDATA
SCLK
CS
1
10
12
14
16
AD7910/AD7920
Figure 9. Normal Mode Operation
THREE-STATE
SDATA
SCLK
CS
1
10
12
14
16
2
Figure 10. Entering Power-Down Mode
INVALID DATA
SDATA
SCLK
CS
1
10
12
14
16
A
1
16
VALID DATA
THE PART IS FULLY
POWERED UP WITH
V
IN
FULLY ACQUIRED
THE PART
BEGINS TO
POWER UP
Figure 11. Exiting Power-Down Mode
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