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參數資料
| 型號： | AD7921AUJ-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 2-Channel, 2.35 V to 5.25 V 250 kSPS, 10-/12-Bit ADCs |
| 中文描述： | 2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
| 封裝： | MO-193BA, TSOT-23 |
| 文件頁數： | 7/28頁 |
| 文件大小： | 312K |
| 代理商： | AD7921AUJ-REEL7 |
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AD7911/AD7921
TIMING SPECIFICATIONS
Guaranteed by characterization.
All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
V
DD
= 2.35 V to 5.25 V; T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 3.
Parameter
Limit at T
MIN
, T
MAX
Unit
f
SCLK1
10
kHz min
2
5
MHz max
t
CONVERT
16 × t
SCLK
14 × t
SCLK
t
QUIET
30
ns min
t
1
15
ns min
t
2
10
ns min
t
33
30
ns max
t
43
45
ns max
t
5
0.4 t
SCLK
ns min
t
6
0.4 t
SCLK
ns min
t
74
10
ns min
t
8
5
ns min
t
9
6
ns min
t
105
30
ns max
10
ns min
t
POWER-UP6
1
μs max
Rev. 0 | Page 7 of 28
Description
AD7921
AD7911
Minimum quiet time required between bus relinquish and start of next conversion
Minimum CS pulse width
CS to SCLK setup time
Delay from CS until DOUT three-state is disabled
DOUT access time after SCLK falling edge
SCLK low pulse width
SCLK high pulse width
SCLK to DOUT valid hold time
DIN setup time prior to SCLK falling edge
DIN hold time after SCLK falling edge
SCLK falling edge to DOUT three-state
SCLK falling edge to DOUT three-state
Power-up time from full power-down
1
Mark/space ratio for SCLK input is 40/60 to 60/40.
2
Minimum f
SCLK
at which specifications are guaranteed.
3
Measured with the load circuit in Figure 2 and defined as the time required for the output to cross V
IH
or V
IL
voltage.
4
Measured with a 50 pF load capacitor.
5
T
10
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
10
, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
6
See the Power-Up Time section.
TIMING DIAGRAMS
0
200
μ
A
I
OL
200
μ
A
I
OH
1.6V
TO OUTPUT
PIN
C
L
50pF
Figure 2. Load Circuit for Digital Output Timing Specifications
0
SCLK
V
IH
V
IL
DOUT
t
4
Figure 3. Access Time after SCLK Falling Edge
0
SCLK
V
IH
V
IL
DOUT
t
7
Figure 4. Hold Time after SCLK Falling Edge
0
SCLK
1.6V
DOUT
t
10
Figure 5. SCLK Falling Edge to DOUT Three-State
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