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參數資料
| 型號： | AD7928BRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 8-Channel, 1 MSPS, 8-/10-/12-Bit ADCs with Sequencer in 20-Lead TSSOP |
| 中文描述： | 8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| 封裝： | MO-153AC, TSSOP-20 |
| 文件頁數： | 24/24頁 |
| 文件大?。?/td> | 607K |
| 代理商： | AD7928BRU |
AD7908/AD7918/AD7928
C
REV. A
APPLICATION HINTS
Grounding and Layout
The AD7908/AD7918/AD7928 have very good immunity to
noise on the power supplies as can be seen by the PSRR versus
Supply Ripple Frequency plot, TPC 3. However, care should
still be taken with regard to grounding and layout.
The printed circuit board that houses the AD7908/AD7918/AD7928
should be designed such that the analog and digital sections are
separated and confined to certain areas of the board. This facili-
tates the use of ground planes that can be separated easily. A
minimum etch technique is generally best for ground planes as
it gives the best shielding. All three AGND pins of the AD7908/
AD7918/AD7928 should be sunk in the AGND plane. Digital
and analog ground planes should be joined at only one place.
If the AD7908/AD7918/AD7928 is in a system where multiple
devices require an AGND to DGND connection, the connec-
tion should still be made at one point only, a star ground point
that should be established as close as possible to the AD7908/
AD7918/AD7928.
Avoid running digital lines under the device as these will couple
noise onto the die. The analog ground plane should be allowed to
run under the AD7908/AD7918/AD7928 to avoid noise coupling.
The power supply lines to the AD7908/AD7918/AD7928 should
use as large a trace as possible to provide low impedance paths
and reduce the effects of glitches on the power supply line. Fast
switching signals, like clocks, should be shielded with digital ground
to avoid radiating noise to other sections of the board, and clock
signals should never be run near the analog inputs. Avoid cross-
over of digital and analog signals. Traces on opposite sides of
the board should run at right angles to each other. This will
reduce the effects of feedthrough through the board. A microstrip
technique is by far the best but is not always possible with a double-
sided board. In this technique, the component side of the board
is dedicated to ground planes while signals are placed on the
solder side.
Good decoupling is also important. All analog supplies should be
decoupled with 10 μF tantalum in parallel with 0.1 μF capacitors to
AGND. To achieve the best from these decoupling components, they
must be placed as close as possible to the device, ideally right up
against the device. The 0.1 μF capacitors should have low Effective
Series Resistance (ESR) and Effective Series Inductance (ESI),
such as the common ceramic types or surface mount types, which
provide a low impedance path to ground at high frequencies to
handle transient currents due to internal logic switching.
Evaluating the AD7908/AD7918/AD7928 Performance
The recommended layout for the AD7908/AD7918/AD7928 is
outlined in the AD7908/AD7918/AD7928 evaluation board.
The evaluation board package includes a fully assembled and tested
evaluation board, documentation, and software for controlling the
board from the PC via the Eval-Board Controller.
The Eval-Board Controller can be used in conjunction with the
AD7908/AD7918/AD7928 evaluation board, as well as many other
Analog Devices evaluation boards ending in the CB designator,
to demonstrate/evaluate the ac and dc performance of the
AD7908/AD7918/AD7928.
The software allows the user to perform ac (fast Fourier transform)
and dc (histogram of codes) tests on the AD7908/AD7918/
AD7928. The software and documentation are on a CD shipped
with the evaluation board.
–24–
OUTLINE DIMENSIONS
20-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-20)
Dimensions shown in millimeters
20
1
11
10
6.40 BSC
4.50
4.40
4.30
PIN 1
6.60
6.50
6.40
SEATING
PLANE
0.15
0.05
0.30
0.19
0.65
BSC
1.20
MAX
0.20
0.09
0.75
0.60
0.45
8
0
COMPLIANT TO JEDEC STANDARDS MO-153AC
COPLANARITY
0.10
Revision History
Location
Page
9/03—Data Sheet changed from REV. 0 to REV. A.
Changes to Figure 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Changes to Reference section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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