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參數資料
| 型號： | AD7940BRJ-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 3mW, 100kSPS, 14-Bit ADC in 6-Lead SOT-23 |
| 中文描述： | 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO6 |
| 封裝： | MO-178AB, SOT-23, 6 PIN |
| 文件頁數： | 13/20頁 |
| 文件大小： | 480K |
| 代理商： | AD7940BRJ-REEL7 |
AD7940
MODES OF OPERATION
The mode of operation of the AD7940 is selected by controlling
the (logic) state of the CS signal during a conversion. There are
two possible modes of operation, normal and power-down. The
point at which CS is pulled high after the conversion has been
initiated will determine whether or not the AD7940 will enter
power-down mode. Similarly, if already in power-down, CS can
control whether the device will return to normal operation or
remain in power-down. These modes of operation are designed
to provide flexible power management options. These options
can optimize the power dissipation/throughput rate ratio for
differing application requirements.
Rev. 0 | Page 13 of 20
NORMAL MODE
This mode provides the fastest throughput rate performance
because the user does not have to worry about the power-up
times with the AD7940 remaining fully powered all the time.
Figure 16 shows the general diagram of the operation of the
AD7940 in this mode.
The conversion is initiated on the falling edge of CS as
described in the Serial Interface section. To ensure that the part
remains fully powered up at all times, CS must remain low until
at least 10 SCLK falling edges have elapsed after the falling edge
of CS. If CS is brought high any time after the 10th SCLK falling
edge, but before the 16th SCLK falling edge, the part will remain
powered up, but the conversion will be terminated and SDATA
will go back into three-state. At least 16 serial clock cycles are
required to complete the conversion and access the complete
conversion result. CS may idle high until the next conversion or
may idle low until CS returns high sometime prior to the next
conversion, effectively idling CS low.
Once a data transfer is complete (SDATA has returned to three-
state), another conversion can be initiated after the quiet time,
t
QUIET
, has elapsed by bringing CS low again.
0
1
12
1 LEADING ZERO + CONVERSION RESULT
CS
SCLK
16
SDATA
Figure 16. Normal Mode Operation
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