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參數(shù)資料
| 型號(hào)： | AD7948BR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | +3.3 V/+5 V Multiplying 12-Bit DACs |
| 中文描述： | PARALLEL, 8 BITS INPUT LOADING, 0.6 us SETTLING TIME, 12-BIT DAC, PDSO20 |
| 封裝： | SOP-20 |
| 文件頁數(shù)： | 10/16頁 |
| 文件大小： | 329K |
| 代理商： | AD7948BR |
AD7943/AD7945/AD7948
REV. B
–10–
AD7948 PIN FUNCTION DESCRIPTIONS
Pin Mnemonic
Description
I
OUT1
AGND
DAC current output terminal 1. Normally terminated at the virtual ground of output amplifier.
Analog Ground Pin. This pin connects to the back gates of the current steering switches. The DAC I
OUT2
terminal is also connected internally to this point.
Digital Ground Pin.
Chip Select Most Significant Byte. Active Low Input. Used in combination with
WR
to load external data into
the input register or in combination with
LDAC
and
WR
to load external data into both input and DAC registers.
Data Format/Data Override. When this input is low, data in the DAC register is forced to one of two override
codes selected by CTRL. When the override signal is removed, the DAC output returns to reflect the value in
the DAC register. With DF/
DOR
high, CTRL selects either a left or right justified input data format. For normal
operation, DF/
DOR
is held high. See Table I.
DGND
CSMSB
DF/
DOR
CTRL
DB7–DB0
LDAC
Control Input. See DF/
DOR
description.
Digital Data Inputs.
Load DAC input, active low. This signal, in combination with others, is used to load the DAC register from
either the input register or the external data bus.
Chip Select Least Significant (LS) Byte. Active Low Input. Used in combination with
WR
to load external data
into the input register or in combination with
WR
and
LDAC
to load external data into both input and DAC
registers.
CSLSB
WR
Write input, active low. This active low signal, in combination with others is used in loading external data into
the AD7948 input register and in transferring data from the input register to the DAC register.
Power supply input. This is nominally +5 V for Normal Mode Operation and +3.3 V to +5 V for Biased Mode
Operation.
DAC reference input.
DAC feedback resistor pin.
V
DD
V
REF
R
FB
Table II. Truth Table for AD7948 Write Operation
WR
CSMSB
CSLSB
LDAC
Function
0
0
0
0
0
1
1
1
0
0
1
X
0
0
1
1
1
X
1
0
1
0
0
X
Load LS Byte to Input Register
Load LS Byte to Input Register and DAC Register
Load MS Byte to Input Register
Load MS Byte to Input Register and DAC Register
Load Input Register to DAC Register
No Data Transfer
Table I. Truth Table for DF/
DOR
CTRL
DF/
DOR
CTRL
Function
0
0
1
1
0
1
0
1
DAC Register Contents Overridden by All 0s
DAC Register Contents Overridden by All 1s
Left-Justified Input Data Selected
Right-Justified Input Data Selected
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