
AD7994/AD7993
–25–
REV. PrF
PRELIMINARY TECHNICAL DATA
Mode 2 -
This mode allows a conversion to be automatically initi-
ated anytime a read operation occurs. In order to use this
mode the command bits C4 - C1 in the Address Pointer
Byte shown in Table II must be programmed.
To select a particular Analog input for conversion in this
mode, then the user must set the corresponding channel
command bit to 1 in the Address Pointer Byte, see Table
XIII. When all four command bits are 0 then this mode is
not in use. A sequence can also be set up for this mode, if
more than one of the command bit in the Address Pointer
Byte are set. The ADC will start converting on the lowest
channel in the sequence and then the next lowest until all
the channels in the sequence have been converted on.
Figure 13 illustrates a two byte read operation from the
Conversion Result Register. This operation would nor-
mally be preceded by a write to the Address Pointer Regis-
ter so that the following read will access the desired
register, in this case the Conversion Result Register Fig-
ure 10. When the contents of the Address Pointer Register
are being loaded, if the command bits C4 to C1 are set
then the AD7994/AD7993 will begin to power up and
convert upon the selected channel(s), power-up will begin
on the fifth SCL falling edge of the Address Point Byte,
see point A Figure 17. Table XIII shows the channel se-
lection in this mode via the command bits, C4 to C1 in
the Address Pointer Register. The wake-up and conversion
time together should take approximately 3
μ
s. Following
this, the AD7994/AD7993 must be addressed again to tell
it that a read operation is required. The read then takes
place from the Conversion Result register. This read will
access the result from the conversion selected via the com-
mand bits. If the Command bits C2, C1 were set to 1,1,
then a four byte read would be necessary. The first read
accesses the data from the conversion on V
IN
1. While this
read takes place, a conversion occurs on V
IN
2. The second
read will access this data from V
IN
2. Figure 18 illustrates
how this mode operates.
When operating the AD7994-1/AD7993-1 in Mode2 with
Hs-Mode, 3.4 MHz SCL, the conversion may not be
complete before the master tries to read the conversion
result, if this is the case the AD7994-1/AD7993-1 will
hold the SCL line low after the read address during the
ACK clock, until the conversion is complete. When the
conversion is complete the AD7994-1/AD7993-1 will
release the SCL line and the master can then read the
conversion result.
Table XIII Address Pointer Byte
C4 C3 C2 C1
P3 P2 P1 P0
Analog Input Channel
0
0
0 0
0 0 0 0
Mode 2 not selected
0
0
0 1
0 0 0 0
Mode 2 Convert on V
IN
1
Mode 2 Convert on V
IN
2
Mode 2 Sequence between V
IN
1 and V
IN
2
Mode 2 Convert on V
IN
3
Mode 2 Sequence between V
IN
1 and V
IN
3
Mode 2 Sequence between V
IN
2 and V
IN
3
Mode 2 Sequence between V
IN
1, V
IN
2 and V
IN
3
Mode 2 Convert on V
IN
4
Mode 2 Sequence between V
IN
1 and V
IN
4
Mode 2 Sequence between V
IN
2 and V
IN
4
Mode 2 Sequence between V
IN
1, V
IN
2 and V
IN
4
Mode 2 Sequence between V
IN
3 and V
IN
4
Mode 2 Sequence between V
IN
1, V
IN
3 and V
IN
4
Mode 2 Sequence between V
IN
2, V
IN
3 and V
IN
4
Mode 2 Sequence between V
IN
1, V
IN
2, V
IN
3 and V
IN
4
0
0
1 0
0 0 0 0
0
0
1 1
0 0 0 0
0
1
0 0
0 0 0 0
0
1
0 1
0 0 0 0
0
1
1 0
0 0 0 0
0
1
1 1
0 0 0 0
1
0
0 0
0 0 0 0
1
0
0 1
0 0 0 0
1
0
1 0
0 0 0 0
1
0
1 1
0 0 0 0
1
1
0 0
0 0 0 0
1
1
0 1
0 0 0 0
1
1
1 0
0 0 0 0
1
1
1 1
0 0 0 0
With the pointer bits set to all 0’s then the next read will
access the results of the conversion Result Register.