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參數(shù)資料
型號: AD7997BRU-1REEL
廠商: ANALOG DEVICES INC
元件分類: ADC
英文描述: 8-Channel, 10- and 12-Bit ADCs with I2CCompatible
中文描述: 8-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20
封裝: MO-153-AC, TSSOP-20
文件頁數(shù): 7/32頁
文件大小: 1056K
代理商: AD7997BRU-1REEL
AD7997/AD7998
I
2
C TIMING SPECIFICATIONS
Guaranteed by initial characterization. All values measured with input filtering enabled. C
B
refers to capacitive load on the bus line. t
r
and
t
f
measured between 0.3 VDD and 0.7 VDD.
Rev. 0 | Page 7 of 32
High speed mode timing specifications apply to the AD7997-1/AD7998-1 only. Standard and fast mode timing specifications apply to
both the AD7997-0/AD7998-0 and the AD7997-1/AD7998-1. See Figure 2. Unless otherwise noted, V
DD
= 2.7 V to 5.5 V; REF
IN
= 2.5 V;
T
A
=T
MIN
to T
MAX
.
Table 3.
AD7997/AD7998 Limit at T
MIN
, T
MAX
Parameter
Conditions
Min
Max
Unit
f
SCL
Standard mode
100
kHz
Fast mode
400
kHz
High speed mode
C
B
= 100 pF max
3.4
MHz
C
B
= 400 pF max
1.7
MHz
t
1
Standard mode
4
μs
Fast mode
0.6
μs
High speed mode
C
B
= 100 pF max
60
ns
C
B
= 400 pF max
120
ns
t
2
Standard mode
4.7
μs
Fast mode
1.3
μs
High speed mode
C
B
= 100 pF max
160
ns
C
B
= 400 pF max
320
ns
t
3
Standard mode
250
ns
Fast mode
100
ns
High speed mode
10
ns
t
41
Standard mode
0
3.45
μs
Fast mode
0
0.9
μs
High speed mode
C
B
= 100 pF max
0
70
2
ns
C
B
= 400 pF max
0
150
ns
t
5
Standard mode
4.7
μs
Fast mode
0.6
μs
High speed mode
160
ns
t
6
Standard mode
4
μs
Fast mode
0.6
μs
High speed mode
160
ns
t
7
Standard mode
4.7
μs
Fast mode
1.3
μs
t
8
Standard mode
4
μs
Fast mode
0.6
μs
High speed mode
160
ns
t
9
Standard mode
1000
ns
Fast mode
20 + 0.1 C
B
300
ns
High speed mode
C
B
= 100 pF max
10
80
ns
C
B
= 400 pF max
20
160
ns
Description
Serial clock frequency
t
HIGH
, SCL high time
t
LOW
, SCL low time
t
SU;DAT
, data setup time
t
HD;DAT
, data hold time
t
SU;STA
, setup time for a repeated start condition
t
HD;STA
, hold time (repeated) start condition
t
BUF
, bus free time between a stop and a start condition
t
SU;STO
, setup time for stop condition
t
RDA
, rise time of SDA signal
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