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參數資料
| 型號： | AD7997BRUZ-13 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 串行ADC |
| 英文描述： | 8-Channel, 10- and 12-Bit ADCs with I2CCompatible |
| 中文描述： | 8通道，10 -和12位ADC與I2CCompatible |
| 文件頁數： | 15/32頁 |
| 文件大小： | 1056K |
| 代理商： | AD7997BRUZ-13 |
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AD7997/AD7998
CIRCUIT INFORMATION
The AD7997/AD7998 are low power, 10- and 12-bit, single-
supply, 8-channel A/D converters. The parts can be operated
from a 2.7 V to 5.5 V supply.
Rev. 0 | Page 15 of 32
The AD7997/AD7998 have an 8-channel multiplexer, an on-
chip track-and-hold, an A/D converter, an on-chip oscillator,
internal data registers, and an I
2
C-compatible serial interface, all
housed in a 20-lead TSSOP. This package offers considerable
space-saving advantages over alternative solutions. The
AD7997/AD7998 require an external reference in the range of
1.2 V to V
DD
.
The AD7997/AD7998 typically remain in a power-down state
while not converting. When supplies are first applied, the parts
come up in a power-down state. Power-up is initiated prior to
a conversion, and the device returns to shutdown when the
conversion is complete. Conversions can be initiated on the
AD7997/AD7998 by pulsing the CONVST signal, using an
automatic cycle interval mode, or a command mode where
wake-up and a conversion occur during a write address
function (see the Modes of Operation section). When the
conversion is complete, the AD7997/AD7998 again enter
shutdown mode. This automatic shutdown feature allows power
saving between conversions. This means any read or write
operation across the I
2
C interface can occur while the device is
in shutdown.
CONVERTER OPERATION
The AD7997/AD7998 are successive approximation analog-to-
digital converters based around a capacitive DAC. Figure 18
and Figure 19 show simplified schematics of the ADC during
the acquisition and conversion phase, respectively. Figure 18
shows the acquisition phase. SW2 is closed and SW1 is in
position A, the comparator is held in a balanced condition,
and the sampling capacitor acquires the signal on V
IN
.
CAPACITIVE
DAC
V
IN
COMPARATOR
CONTROL
LOGIC
SW1
A
B
SW2
AGND
0
Figure 18. ADC Acquisition Phase
At the beginning of a conversion, SW2 opens and SW1 moves
to position B, causing the comparator to become unbalanced, as
shown in Figure 19. The input is disconnected once the con-
version begins. The control logic and the capacitive DAC are
used to add and subtract fixed amounts of charge from the
sampling capacitor to bring the comparator back into a
balanced condition. When the comparator is rebalanced, the
conversion is complete. The control logic generates the ADC
output code. Figure 20 shows the ADC transfer characteristic.
V
IN
COMPARATOR
CONTROL
LOGIC
SW1
A
B
SW2
AGND
CAPACITIVE
DAC
0
Figure 19. ADC Conversion Phase
ADC Transfer Function
The output coding of the AD7997/AD7998 is straight binary.
The designed code transitions occur at successive integer LSB
values (1 LSB, 2 LSB, and so on). The LSB size is REF
IN
/1024 for
the AD7997 and REF
IN
/4096 for the AD7998. Figure 20 shows
the ideal transfer characteristic for the AD7997/AD7998.
000...000
A
ANALOG INPUT
0V TO REF
IN
111...111
111...110
000...001
000...010
111...000
011...111
AGND + 1LSB
+REF
IN
– 1LSB
AD7998 1LSB = REF
IN
/4096
0
AD7997 1LSB = REF
IN
/1024
Figure 20. AD7997/AD7998 Transfer Characteristic
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| AD7997BRUZ-1REEL | 功能描述:IC ADC 10BIT 8CHAN I2C 20TSSOP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 標準包裝:2,500 系列:- 位數:16 采樣率（每秒）:15 數據接口:MICROWIRE?，串行，SPI? 轉換器數目:1 功率耗散（最大）:480µW 電壓電源:單電源 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:38-WFQFN 裸露焊盤 供應商設備封裝:38-QFN（5x7） 包裝:帶卷 (TR) 輸入數目和類型:16 個單端，雙極；8 個差分，雙極 配用:DC1011A-C-ND - BOARD DELTA SIGMA ADC LTC2494 |
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| AD7998 | 制造商:AD 制造商全稱:Analog Devices 功能描述:8-Channel, 10- and 12-Bit ADCs with I2CCompatible |
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