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參數資料
| 型號： | AD7998BRUZ-03 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 串行ADC |
| 英文描述： | 8-Channel, 10- and 12-Bit ADCs with I2CCompatible |
| 中文描述： | 8通道，10 -和12位ADC與I2CCompatible |
| 文件頁數： | 22/32頁 |
| 文件大小： | 1056K |
| 代理商： | AD7998BRUZ-03 |
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AD7997/AD7998
CYCLE TIMER REGISTER
The cycle timer register is an 8-bit, read/write register that
stores the conversion interval value for the automatic cycle
interval mode of the AD7997/AD7998 (see the Modes of
Operation section). D5 to D3 of the cycle timer register are
unused and should contain 0s at all times. On power-up, the
cycle timer register contains all 0s, thus disabling automatic
cycle operation of the AD7997/AD7998. To enable automatic
cycle mode, the user must write to the cycle timer register,
selecting the required conversion interval by programming Bits
D2 to D0. Table 23 shows the structure of the cycle timer
register, while Table 24 shows how the bits in this register are
decoded to provide various automatic sampling intervals.
Table 23. Cycle Timer Register and Defaults at Power-Up
D7
D6
D5
D4
Sample
Delay
Delay
0
0
0
0
Table 24. Cycle Timer Intervals
Typical Conversion Interval
(T
CONVERT
= Conversion Time)
0
0
0
Mode Not Selected
0
0
1
T
CONVERT
× 32
0
1
0
T
CONVERT
× 64
0
1
1
T
CONVERT
× 128
1
0
0
T
CONVERT
× 256
1
0
1
T
CONVERT
× 512
1
1
0
T
CONVERT
× 1024
1
1
1
T
CONVERT
× 2048
Rev. 0 | Page 22 of 32
D3
D2
Cyc
Bit2
0
D1
Cyc
Bit1
0
D0
Cyc
Bit0
0
Bit Trial
0
0
0
0
D2
D1
D0
SAMPLE DELAY AND BIT TRIAL DELAY
It is recommended that no I
2
C bus activity occurs when a
conversion is taking place. However, if this is not possible, for
example when operating in Mode 2 or Mode 3, then in order to
maintain the performance of the ADC, Bits D7 and D6 in the
cycle timer register are used to delay critical sample intervals
and bit trials from occurring while there is activity on the I
2
C
bus. This results in a quiet period for each bit decision. In
certain cases where there is excessive activity on the interface
lines, this may have the effect of increasing the overall
conversion time. However, if bit trial delays extend longer than
1 μs, the conversion terminates.
When Bits D7 and D6 are both 0, the bit trial and sample
interval delaying mechanism is implemented. The default
setting of D7 and D6 is 0. To turn off both delay mechanisms,
set D7 and D6 to 1.
Table 25. Cycle Timer Register and Defaults at Power-up
D7
D6
D5
D4
Sample
Delay
Delay
0
0
0
0
D3
D2
Cyc
Bit 2
0
D1
Cyc
Bit 1
0
D0
Cyc
Bit 0
0
Bit Trial
0
0
0
0
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