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參數資料
| 型號： | AD8011AR-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運動控制電子 |
| 英文描述： | 300 MHz, 1 mA Current Feedback Amplifier |
| 中文描述： | OP-AMP, 6000 uV OFFSET-MAX, PDSO8 |
| 封裝： | SOIC-8 |
| 文件頁數： | 12/16頁 |
| 文件大?。?/td> | 219K |
| 代理商： | AD8011AR-REEL |
REV. B
–12–
AD8011
11
10
9
8
7
5
4
3
6
2
1
1 10 100 500
FREQUENCY
–
MHz
G
–
R
F
= 1k
R
F
= 750
V
= 5V
G = +2
V
IN
= 200mV
Figure 35. Flatness vs. Feedback
Output pin and external component capacitance (designated
C
L
) will further extend the devices BW and can also cause peak-
ing below and above the CLBW if too high. In the time domain,
poor step settling characteristics (ringing up to about 2 GHz
and excessive overshoot) can result. For high C
L
values greater
than about 5 pF an external series
“
damping
”
resistor is recom-
mended. See section on Settling Time vs. C
L
. For light loads,
any output capacitance will reflect back on A2
’
s output (Z2 of
buffer A3) as both added capacitance near the CLBW (CLBW
> f
T
/B) and eventually negative resistance at much higher fre-
quencies. These added effects are proportional to the load C.
This reflected capacitance and negative resistance has the effect
of both reducing A2/s phase margin and causing high frequency
“
L
×
C
”
peaking respectively. Using an external series resistor
(as specified above) reduces these unwanted effects by creating a
reflected zero to A2
’
s output which will reduce the peaking and
eliminate ringing. For heavy resistive loads, relatively more Load
C would be required to cause these same effects.
High inductive parasitics, especially on the supplies and inverting/
noninverting inputs, can cause modulated low level R
F
ringing
on the output in the transient domain. Again, proper R
F
compo-
nent and board layout practices need to be observed. Relatively
high parasitic lead inductance (roughly L >15 nh) can result in
L
×
C underdamped ringing. Here L/C means all associated
input pin, external component and leadframe strays including
collector to substrate device capacitance. In the ac domain, this
L
×
C resonance effect would typically not appear in the pass-
band of the amplifier but would appear in the open loop re-
sponse at frequencies well above the CLBW of the amplifier.
40
30
20
0
10
15
20
25
C
L
–
pF
10
R
S
–
5
Figure 34. Recommended R
SERIES
vs. Capacitive Load for
≤
30 ns Settling to 0.1%
OPTIMIZING FLATNESS
As mentioned, the ac transfer equations above are based on
a simplified single pole model. Due to the devices internal para-
sitics (primarily CP1/CP1B and CP2 in Figure 28) and
external package/board parasites (partially represented in Figure
34) the computed BW, using the V
O
(s) equation above, typi-
cally will be lower than the AD8011
’
s measured small signal
BW. See data sheet Bode plots.
With internal parasitics included only, the BW is extended do to
the complex pole pairs created primarily by CP1/CP2B and CP2
versus the single-pole assumption shown above. This results in a
“
design controlled
”
closed-loop damping factor (
ζ)
of nominally
0.6 resulting in the CLBW increasing by approximately 1.3
×
higher than the computed single pole value above
for optimized
external gains of +2/–1
! As external noninverting gain (G) is
increased, the actual closed-loop bandwidth vs. the computed
single pole ac response is in closer agreement.
Inverting pin and external component capacitance (designated
C
P
) will further extend the CLBW do the closed loop zero cre-
ated by C
P
and R
N
R
F
when operating in the noninverting mode.
Using proper R
F
component and layout techniques (see layout
section) this capacitance should be about 1.5 pF. This results in a
further incremental BW increase of almost 2
×
(versus the com-
puted value) for G = +1 decreasing and approaching its complex
pole pair BW for gains approaching +6 or higher. As previously
discussed, the single-pole response begins to correlate well. Note
that a pole is also created by 1/2 g
mf
and C
P
which prevents the
AD8011 from becoming unstable. This parasitic has the greatest
effect on BW and peaking for low positive gains as the data
sheet Bode plots clearly show. For inverting operation, C
P
has
relatively much less effect on CLBW variation.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD8011AR-REEL7 | 功能描述:IC OPAMP CF LP LDIST 30MA 8SOIC RoHS:否 類別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:- 標準包裝:2,500 系列:- 放大器類型:通用 電路數:1 輸出類型:滿擺幅 轉換速率:0.11 V/µs 增益帶寬積:350kHz -3db帶寬:- 電流 - 輸入偏壓:4nA 電壓 - 輸入偏移:20µV 電流 - 電源:260µA 電流 - 輸出 / 通道:20mA 電壓 - 電源，單路/雙路(±):2.7 V ~ 36 V，±1.35 V ~ 18 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:8-SO 包裝:帶卷 (TR) |
| AD8011ARZ | 功能描述:IC OPAMP CF LP LDIST 30MA 8SOIC RoHS:是 類別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:- 標準包裝:2,500 系列:- 放大器類型:通用 電路數:4 輸出類型:- 轉換速率:0.6 V/µs 增益帶寬積:1MHz -3db帶寬:- 電流 - 輸入偏壓:45nA 電壓 - 輸入偏移:2000µV 電流 - 電源:1.4mA 電流 - 輸出 / 通道:40mA 電壓 - 電源，單路/雙路(±):3 V ~ 32 V，±1.5 V ~ 16 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:14-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:14-TSSOP 包裝:帶卷 (TR) 其它名稱:LM324ADTBR2G-NDLM324ADTBR2GOSTR |
| AD8011ARZ | 制造商:Analog Devices 功能描述:Operational Amplifier (Op-Amp) IC 制造商:Analog Devices 功能描述:IC, OP-AMP, 300MHZ, 3500V/ us, SOIC-8 |
| AD8011ARZ | 制造商:Analog Devices 功能描述:IC AMPLIS |
| AD8011ARZ-REEL | 功能描述:IC OPAMP CF LP LDIST 30MA 8SOIC RoHS:是 類別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:- 其它有關文件:Automotive Product Guide 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 放大器類型:通用 電路數:1 輸出類型:滿擺幅 轉換速率:3 V/µs 增益帶寬積:10MHz -3db帶寬:- 電流 - 輸入偏壓:1pA 電壓 - 輸入偏移:70µV 電流 - 電源:2.5mA 電流 - 輸出 / 通道:48mA 電壓 - 電源，單路/雙路(±):2.7 V ~ 5.5 V，±1.35 V ~ 2.75 V 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應商設備封裝:SOT-6 包裝:Digi-Reel® 其它名稱:MAX4475AUT#TG16DKR |
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