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參數資料
| 型號： | AD8012AR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 音頻／視頻放大 |
| 英文描述： | SB 2- 7/9 |
| 中文描述： | 1 CHANNEL, VIDEO AMPLIFIER, PDSO8 |
| 封裝： | MS-012AA, SOIC-8 |
| 文件頁數： | 12/15頁 |
| 文件大小： | 414K |
| 代理商： | AD8012AR |
AD8012
–12–
REV. A
APPLICATIONS
Line Driving for HDSL
High Bitrate Digital Subscriber Line (HDSL) is becoming
popular as a means of providing full duplex data communication
at rates up to 1.544 MBPS or 2.048 MBPS over moderate dis-
tances via conventional telephone twisted pair wires. Traditional
T1 (E1 in Europe) requires repeaters every 3,000 feet to 6,000
feet to boost the signal strength and allow transmission over
distances of up to 12,000 feet. In order to achieve repeaterless
transmission over this distance, an HDSL modem requires
transmitted power level of +13.5 dBm (assuming a line imped-
ance of 135
).
HDSL uses the Two Binary/One Quaternary line code (2B1Q).
A sample 2B1Q waveform is shown in Figure 41. The digital bit
stream is broken up into groups of two bits. Four analogue
voltages (called quaternary symbols) are used to represent the
four possible combinations of two bits. These symbols are as-
signed arbitrary names +3, +1, –1 and –3. The corresponding
voltage levels are produced by a DAC that is usually part of an
Analog Front End Circuit (AFEC). Before being applied to the
line, the DAC output is low-pass filtered and acquires the sinu-
soidal form shown in Figure 41. Finally, the filtered signal is
applied to the line driver. The line voltages that correspond to
the quaternary symbols +3, +1, –1 and –3 are 2.64 V, 0.88 V,
–0.88 V and –2.64 V. This gives a peak-to-peak line voltage of
5.28 V.
VOLTAGE
+3 2.64V
+1 0.88V
–1 –0.88V
–3 –2.64V
SYMBOL
NAME
DAC
OUTPUT
FILTERED
OUTPUT
TO LINE
DRIVER
–1
01
+3
10
+1
11
–3
00
–3
00
+1
11
+3
10
–3
00
–1
01
–1
01
+1
11
–1
01
–3
00
Figure 41. Time Domain Representation of a HDSL Signal
Many of the elements of a classic differential line driver are
shown in the HDSL line driver in Figure 42. A 6 V peak-to-
peak differential signal is applied to the input. The differential
gain of the amplifier (1+2 R
F
/R
G
) is set to +2, so the resulting
differential output signal is 12 V p-p.
As is normal in telephony applications, a transformer galvani-
cally isolates the differential amplifier from the line. In this case
a 1:1 turns ratio is used. In order to correctly terminate the line,
it is necessary to set the output impedance of the amplifier to be
equal to the impedance of the line being driven (135
in this
case). Because the transformer has a turns ratio of 1:1, the im-
pedance reflected from the line is equal to the line impedance
of 135
(R
REFL
= R
LINE
/Turns Ratio
2
). As a result, two 66.5
resistors correctly terminate the line.
6V p-p
12V p-p
1:1
+5V
–5V
R
F
750
V
R
F
750
V
R
G
1.5k
V
1/2
AD8012
1/2
AD8012
0.1
m
F
0.1
m
F
66.5
V
66.5
V
6V p-p
1:1
135
V
TO
RECEIVER
CIRCUITRY
TO
RECEIVER
CIRCUITRY
GAIN = +2
UP TO
12,000 FEET
+
–
Figure 42. Differential for HDSL Applications
The immediate effect of back-termination is that the signal from
the amplifier is halved before being applied to the line. This
doubles the power the amplifier must deliver. However, the
back-termination resistors also play an important second role.
Full-duplex data transmission systems like HDSL simulta-
neously transmit data in both directions. As a result, the signal
on the line and across the back termination resistors is the com-
posite of the transmitted and received signal. The termination
resistors are used to tap off this signal and feed it to the receive
circuitry. Because the receive circuitry “knows” what is being
transmitted, the transmitted data can be subtracted from the
digitized composite signal to reveal the received data.
Driving a line with a differential signal offers a number of ad-
vantages compared to a single-ended drive. Because the two
outputs are always 180 degrees out of phase relative to one
another, the differential signal output is double the output am-
plitude of either of the op amps. As a result, the differential
amplifier can have a peak-to-peak swing of 16 V (each op amp
can swing to
±
4 V), even though the power supply is
±
5 V.
In addition to this, even-order harmonics (2nd, 4th, 6th, etc.) of
the two single-ended outputs tend to cancel out one another, so
the Total Harmonic Distortion (quadratic sum of all harmonics)
decreases compared to the single-ended case, even as the signal
amplitude is doubled. This is particularly advantageous for the
case of the second harmonic. As it is very close to the funda-
mental, filtering becomes difficult. In this application, the THD
is dominated by the third harmonic which is 65 dB below the
carrier (i.e., Spurious Free Dynamic Range = –65 dBc).
Differential line driving also helps to preserve the integrity of
the transmitted signal in the presence of Electro-Magnetic In-
terference (EMI). EMI tends to induce itself equally on to both
the positive and negative signal line. As a result, a receiver with
good common-mode rejection, will amplify the original signal
while rejecting induced (common-mode) EMI.
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相關代理商/技術參數 |
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|---|---|
| AD8012AR | 制造商:Analog Devices 功能描述:AMPLIFIER ((NW)) |
| AD8012AR-EBZ | 功能描述:BOARD EVAL FOR AD8012AR RoHS:是 類別:編程器，開發系統 >> 評估板 - 運算放大器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- |
| AD8012ARM | 功能描述:IC OPAMP CF DUAL LP 125MA 8MSOP RoHS:否 類別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:- 標準包裝:50 系列:- 放大器類型:J-FET 電路數:2 輸出類型:- 轉換速率:13 V/µs 增益帶寬積:3MHz -3db帶寬:- 電流 - 輸入偏壓:65pA 電壓 - 輸入偏移:3000µV 電流 - 電源:1.4mA 電流 - 輸出 / 通道:- 電壓 - 電源，單路/雙路(±):7 V ~ 36 V，±3.5 V ~ 18 V 工作溫度:-40°C ~ 85°C 安裝類型:通孔 封裝/外殼:8-DIP（0.300"，7.62mm） 供應商設備封裝:8-PDIP 包裝:管件 |
| AD8012ARM-EBZ | 功能描述:BOARD EVAL FOR AD8012ARM RoHS:是 類別:編程器，開發系統 >> 評估板 - 運算放大器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- |
| AD8012ARM-REEL | 制造商:Analog Devices 功能描述:ADSL Driver Dual 8-Pin MSOP T/R |
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